公开(公告)号：US07321950B2

公开(公告)日：2008-01-22

申请号：US11050021

申请日：2005-02-03

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC: G06F12/00

CPC classification number: G06F13/161 ,  G06F13/1647

Abstract: A method and apparatus for managing write-to-read turnarounds in an early read after write memory system are presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract translation: 提出了一种用于在写入存储器系统之后的早期读取中管理写入到读取周转的方法和装置。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07275137B2

公开(公告)日：2007-09-25

申请号：US10970458

申请日：2004-10-21

Applicant: Mark David Bellows

Inventor： Mark David Bellows

IPC: G06F12/00

CPC classification number: G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A method, an apparatus, and a computer program are provided for controlling a transmission enable (TX_ENA) signal. In Extreme Data Rate (XDR™) Dynamic Random Access Memories (DRAMs) or XDRAMS, there is a requirement that a TX_ENA signal remain logic high for a few cycles before data transmission, and, when TX_ENA transitions to logic low, TX_ENA remain logic low for a few cycles. However, maintaining this timing can be difficult with back-to-back writes. Therefore, additional logic is employed within XDRAM memory controllers to insure that TX_ENA does not violate system requirements by allowing TX_ENA to remain logic high between successive writes or when the system is devoid of commands.

Abstract translation: 提供了一种用于控制发送使能（TX_ENA）信号的方法，装置和计算机程序。 在极端数据速率（XDR TM））动态随机存取存储器（DRAM）或XDRAMS中，要求TX_ENA信号在数据传输之前几个周期保持逻辑高电平，并且当TX_ENA转换到逻辑低电平时TX_ENA保持 逻辑低电平几个周期。 然而，通过背靠背的写入，保持这个时机可能是困难的。 因此，在XDRAM存储器控制器中采用额外的逻辑，以确保TX_ENA不会在连续写入之间或当系统没有命令时允许TX_ENA保持逻辑高电平而违反系统要求。

公开(公告)号：US07925823B2

公开(公告)日：2011-04-12

申请号：US11875469

申请日：2007-10-19

Applicant: Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Kent Harold Haselhorst ,  Paul Allen Ganfield ,  Tolga Ozguner

IPC: G06F12/00

CPC classification number: G11C29/02 ,  G11C29/022 ,  G11C29/028

Abstract: A mechanism is provided to reuse functional data buffers. With Extreme Data Rate (XDR™) Dynamic Random Access Memory (DRAM), test patterns are employed to dynamically calibrate data with the clock. To perform this task, data buffers are employed to store data and commands for the calibration patterns. However, there are different procedures and requirements for transmission and reception calibrations. Hence, to reduce the amount of hardware needed to perform transmission and reception calibrations, the data buffers employ additional front end circuitry to reuse the buffers for both tasks.

Abstract translation: 提供了重用功能数据缓冲器的机制。 使用极限数据速率（XDR™）动态随机存取存储器（DRAM），采用测试模式来动态校准数据与时钟。 为了执行此任务，采用数据缓冲器来存储校准模式的数据和命令。 然而，发送和接收校准有不同的程序和要求。 因此，为了减少执行发送和接收校准所需的硬件数量，数据缓冲器使用附加的前端电路来为这两个任务重新使用缓冲器。

公开(公告)号：US07752379B2

公开(公告)日：2010-07-06

申请号：US12349240

申请日：2009-01-06

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  Kent Harold Haselhorst ,  Ryan Abel Heckendorf ,  Tolga Ozguner

IPC: G06F12/06 ,  G06F13/00 ,  G06F13/28

CPC classification number: G06F13/161 ,  G06F13/1647

Abstract: Managing write-to-read turnarounds in an early read after write memory system is presented. Memory controller logic identifies a write operation's bank set, allows a different bank set read operation to issue prior to the write operation's completion, and allows a same bank set read operation to issue once the write operation completes. The memory controller includes operation counter logic, operation selection logic, operation acceptance logic, command formatting logic, and memory interface logic. The operation counter logic receives new-operation-related signals from the operation acceptance logic and, in turn, provides signals to the operation selection logic and the operation acceptance logic as to when to issue a read operation that corresponds to either an even DRAM bank or an odd DRAM bank.

Abstract translation: 介绍了在写入内存系统之后的早期读取中管理写入阅读的周转时间。 存储器控制器逻辑识别写入操作的存储体组，允许在写入操作完成之前发出不同的存储体读取操作，并且一旦写入操作完成，就允许执行相同的存储体读取操作。 存储器控制器包括操作计数器逻辑，操作选择逻辑，操作接受逻辑，命令格式化逻辑和存储器接口逻辑。 操作计数器逻辑接收来自操作接受逻辑的新操作相关信号，并且继而向操作选择逻辑和操作接受逻辑提供关于什么时候发出对应于偶数DRAM组的读操作的信​​号 一个奇怪的DRAM银行。

公开(公告)号：US07631154B2

公开(公告)日：2009-12-08

申请号：US11849548

申请日：2007-09-04

Applicant: Mark David Bellows

Inventor： Mark David Bellows

IPC: G06F12/00

CPC classification number: G11C7/1072 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/4076 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: A mechanism provided for controlling a transmission enable (TX_ENA) signal. The mechanism generates a queue of bits to track a sequence of commands and provides the transmit enable signal if the queue is empty. If an entry at a top of the queue indicates a write command, the mechanism provides the transmit enable signal for a predetermined number of cycles before the transmit enable signal is needed and until write data associated with the entry is transmitted, whereupon the entry is removed from the queue. If the entry at the top of the queue does not indicate a write command, the mechanism discontinues the transmit enable signal and removing the entry from the queue.

Abstract translation: 一种用于控制发送使能（TX_ENA）信号的机制。 该机制产生一个比特队列来跟踪一系列命令，如果队列为空，则提供发送使能信号。 如果队列顶部的条目指示写入命令，则该机制在需要发送使能信号之前提供预定数量的周期的发送使能信号，并且直到发送与该条目相关联的写入数据，从而该条目被移除 从排队。 如果队列顶部的条目不表示写入命令，则该机制将中断发送使能信号并从队列中删除该条目。

公开(公告)号：US07283562B2

公开(公告)日：2007-10-16

申请号：US10255513

申请日：2002-09-26

Applicant: Mark David Bellows

Inventor： Mark David Bellows

IPC: H04J3/16

CPC classification number: H04L47/10 ,  H04L41/0896 ,  H04L43/0882 ,  H04L47/12 ,  H04L47/326

Abstract: A method and apparatus are provided for scaling an input bandwidth for bandwidth allocation technology. An original bandwidth count value of an input flow is received. A bandwidth scalar constant is provided and used for scaling the received original bandwidth count value to provide a scaled bandwidth value between zero and one. The scaled bandwidth value is stored and used for calculating a transmit probability for the input flow.

Abstract translation: 提供了一种用于缩放用于带宽分配技术的输入带宽的方法和装置。 接收输入流的原始带宽计数值。 提供带宽标量常数并用于缩放所接收的原始带宽计数值，以提供零和一之间的缩放带宽值。 缩放的带宽值被存储并用于计算输入流的发送概率。

公开(公告)号：US07206284B2

公开(公告)日：2007-04-17

申请号：US10305745

申请日：2002-11-27

Applicant: Mark David Bellows

Inventor： Mark David Bellows

IPC: G01R31/08 ,  H04L12/28 ,  H04J3/16

CPC classification number: H04L47/20 ,  H04L47/10 ,  H04L47/12 ,  H04L47/2441 ,  H04L47/31 ,  H04L47/326

Abstract: A method and apparatus are provided for implementing automatic congestion avoidance for differentiated service flows in a communications network. A bandwidth control signal representing congestion information is identified. Responsive to the identified bandwidth control signal, dual transmit probabilities are calculated for each flow. The dual transmit probabilities include a first transmit probability for a first color and a first transmit probability for a second color. A marked color for a packet is identified. The marked packet color and the calculated dual transmit probabilities are selectively utilized for making a packet discard determination.

Abstract translation: 提供了一种用于在通信网络中实现差分服务流的自动拥塞避免的方法和装置。 识别表示拥塞信息的带宽控制信号。 响应于所识别的带宽控制信号，为每个流量计算双重传输概率。 双重传输概率包括用于第一颜色的第一传输概率和第二颜色的第一传输概率。 识别分组的标记颜色。 选择性地使用标记分组颜色和计算出的双重传输概率进行分组丢弃确定。

公开(公告)号：US07558908B2

公开(公告)日：2009-07-07

申请号：US11860209

申请日：2007-09-24

Applicant: Mark David Bellows ,  Ryan Abel Heckendorf

Inventor： Mark David Bellows ,  Ryan Abel Heckendorf

IPC: G06F13/00

CPC classification number: G06F13/1684 ,  G06F13/1689

Abstract: A structure of sequencers, a method, and a computer program are provided for performing initial and periodic calibrations in an XDR™ memory system. A memory controller that performs these calibrations is divided into identical, independent halves, with each half containing a Current/Impedance Calibration (i/z Cal) sequencer and six Bank sequencers. The i/z Cal sequencer contains three pathways that perform the XIO current and termination calibrations, and the XDR™ DRAM current and termination impedance calibrations. Each Bank sequencer contains normal read and write operation pathways that are reused to accomplish receive setup, receive hold, transmit setup, transmit hold, XIO receive, and XIO transmit timing calibrations. Initial and periodic calibrations are necessary to ensure the precise transfer of data between the XIOs and the XDR™ DRAMs.

Abstract translation: 提供了定序器的结构，方法和计算机程序，用于在XDR TM存储器系统中执行初始和周期性校准。 执行这些校准的存储器控​​制器被分成相同的独立半部，每个半部分包含电流/阻抗校准（i / z Cal）定序器和六个音序器。 i / z Cal序列器包含执行XIO电流和终止校准的三个路径，以及XDR（TM）DRAM电流和终端阻抗校准。 每个Bank序列器都包含正常的读写操作路径，用于实现接收建立，接收保持，发送设置，发送保持，XIO接收和XIO发送定时校准。 必须进行初始和周期性校准，以确保XIO和XDR（TM）DRAM之间数据的精确传输。

公开(公告)号：US20080183916A1

公开(公告)日：2008-07-31

申请号：US11668531

申请日：2007-01-30

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  Ryan Abel Heckendorf ,  John David Irish ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  Ryan Abel Heckendorf ,  John David Irish ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

IPC: G06F13/00

CPC classification number: G06F11/106

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a processor adapted to issue a command complying with a first protocol; (2) providing a memory coupled to the processor and accessible by a command complying with a second protocol; (3) employing a plurality of scrub commands complying with the second protocol to check respective portions of the memory for errors, wherein each scrub command complying with the second protocol is a converted version of a scrub command complying with the first protocol issued by the processor and the respective portions are non-sequential; and (4) refreshing bits stored in the entire memory within a predetermined time period. Numerous other aspects are provided.

Abstract translation: 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供适于发出符合第一协议的命令的处理器; （2）提供耦合到所述处理器的存储器，并且可通过符合第二协议的命令来访问; （3）采用符合第二协议的多个擦除命令来检查存储器的相应部分的错误，其中符合第二协议的每个擦除命令是符合由处理器发出的第一协议的擦除命令的转换版本 并且各部分是非顺序的; 和（4）在预定时间段内刷新存储在整个存储器中的位。 提供了许多其他方面。

公开(公告)号：US20080168298A1

公开(公告)日：2008-07-10

申请号：US11620104

申请日：2007-01-05

Applicant: Mark David Bellows ,  Paul Allen Ganfield ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

Inventor： Mark David Bellows ,  Paul Allen Ganfield ,  David Alan Norgaard ,  Ibrahim Abdel-Rahman Ouda ,  Tolga Ozguner

IPC: G06F12/00 ,  G06F1/08

CPC classification number: G11C7/10 ,  G11C2207/2254

Abstract: In a first aspect, a first method of interfacing a processor and memory is provided. The first method includes the steps of (1) providing a computer system including (a) a memory; (b) a processor adapted to issue a functional command to the memory; (c) a translation chip; (d) a first link adapted to couple the processor to the translation chip; and (e) a second link adapted to couple the translation chip to the memory; (2) calibrating the first link using the translation chip; and (3) while calibrating the first link, calibrating the second link using the translation chip. Numerous other aspects are provided.

Abstract translation: 在第一方面，提供了一种接口处理器和存储器的第一种方法。 第一种方法包括以下步骤：（1）提供一种包括（a）存储器的计算机系统; （b）适于向存储器发出功能命令的处理器; （c）翻译芯片; （d）适于将所述处理器耦合到所述翻译芯片的第一链接; 和（e）适于将所述翻译芯片耦合到所述存储器的第二链接; （2）使用翻译芯片校准第一链接; 和（3）在校准第一链路的同时，使用转换芯片校准第二链路。 提供了许多其他方面。