公开(公告)号：US07904943B2

公开(公告)日：2011-03-08

申请号：US11027913

申请日：2004-12-28

Applicant: Dennis M. O'Connor ,  Mark N. Fullerton ,  Ray Richardson

Inventor： Dennis M. O'Connor ,  Mark N. Fullerton ,  Ray Richardson

IPC: G06F7/04

CPC classification number: G06F21/74 ,  G06F21/79

Abstract: A storage controller includes a command pointer register. The command pointer register points to a chain of commands in memory, and also includes a security status field to indicate a security status of the first command in the command chain. Each command in the command chain may also include a security status field that indicates the security status of the following command in the chain.

Abstract translation: 存储控制器包括命令指针寄存器。 命令指针寄存器指向存储器中的一系列命令，并且还包括用于指示命令链中的第一命令的安全状态的安全状态字段。 命令链中的每个命令还可以包括指示链中以下命令的安全状态的安全状态字段。

公开(公告)号：US07827323B2

公开(公告)日：2010-11-02

申请号：US11953552

申请日：2007-12-10

Applicant: Ofer Bar-Shalom ,  Mark N. Fullerton ,  Alon Tsafrir

Inventor： Ofer Bar-Shalom ,  Mark N. Fullerton ,  Alon Tsafrir

IPC: G06F13/28 ,  G06F13/24

CPC classification number: G06F13/28

Abstract: A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.

Abstract translation: 主机设备包括外围控制模块，其包括从第一存储器接收数据的第一存储器寄存器和与第一存储器通信的直接存储器访问（DMA）模块。 主机设备还包括从第一存储器接收数据的主机控制模块。 主机设备还包括与第一存储器寄存器，主机控制模块和包括第一存储器阵列的第二存储器通信的DMA控制模块。 DMA控制模块将第一存储器阵列的内容与存储器寄存器的内容进行比较，并且基于比较控制从第一存储器到外围控制模块的数据传输。

公开(公告)号：US20100272162A1

公开(公告)日：2010-10-28

申请号：US12604193

申请日：2009-10-22

Applicant: Claire Simeon ,  Ronak Patel ,  Mark N. Fullerton

Inventor： Claire Simeon ,  Ronak Patel ,  Mark N. Fullerton

IPC: H04B1/38

CPC classification number: G06F13/385

Abstract: A synchronous serial programmable interface that programmably defines a plurality of frame definitions in which each frame definition provides signal timing for a corresponding frame used in serial data transfer. A sequencer module is used to provide a plurality of instructions, in which each instruction, when executed, obtains a frame definition from the plurality of frame definitions. Then a task scheduler selects a scheduled task from a plurality of tasks that are used in transferring data. The particular task selects one or more instructions from the plurality of instructions and obtains one or more frame definitions specified by the instruction or instructions to establish one or more frames that are used in transferring the data.

Abstract translation: 一种可编程定义多个帧定义的同步串行可编程接口，其中每个帧定义为串行数据传输中使用的相应帧提供信号定时。 定序器模块用于提供多个指令，其中每个指令在执行时从多个帧定义中获得帧定义。 然后，任务调度器从用于传送数据的多个任务中选择调度任务。 特定任务从多个指令中选择一个或多个指令，并且获得由指令或指令指定的一个或多个帧定义，以建立用于传送数据的一个或多个帧。

公开(公告)号：US20080140878A1

公开(公告)日：2008-06-12

申请号：US11953552

申请日：2007-12-10

Applicant: Ofer Bar-Shalom ,  Mark N. Fullerton ,  Alon Tsafrir

Inventor： Ofer Bar-Shalom ,  Mark N. Fullerton ,  Alon Tsafrir

IPC: G06F13/28

CPC classification number: G06F13/28

Abstract: A host device includes a peripheral control module that includes a first memory register that receives data from a first memory and a direct memory access (DMA) module that communicates with the first memory. The host device also includes a host control module that receives data from the first memory. The host device also includes a DMA control module that communicates with the first memory register, the host control module and a second memory that includes a first memory array. The DMA control module compares contents of the first memory array to contents of the memory register and controls transfers of data from the first memory to the peripheral control module based on the comparison.

Abstract translation: 主机设备包括外围控制模块，其包括从第一存储器接收数据的第一存储器寄存器和与第一存储器通信的直接存储器访问（DMA）模块。 主机设备还包括从第一存储器接收数据的主机控制模块。 主机设备还包括与第一存储器寄存器，主机控制模块和包括第一存储器阵列的第二存储器通信的DMA控制模块。 DMA控制模块将第一存储器阵列的内容与存储器寄存器的内容进行比较，并且基于比较控制从第一存储器到外围控制模块的数据传输。

公开(公告)号：US08677457B2

公开(公告)日：2014-03-18

申请号：US12026840

申请日：2008-02-06

Applicant: Mark N. Fullerton

Inventor： Mark N. Fullerton

IPC: G06F21/00

CPC classification number: H04L63/10 ,  G06F21/53 ,  G06F21/54 ,  G06F21/74

Abstract: A method and apparatus configure a trusted domain and a plurality of isolated domains in a processor core. Each isolated domain is assigned a unique domain identifier. One or more resources are associated with each isolated domain. The associations are stored as permissions to access physical addresses of resources. Code to be executed by a hardware device is assigned to one of the isolated domains. The domain identifier for the assigned isolated domain is written to the hardware device. When the hardware device executes the code, each instruction is logically tagged with the domain identifier written to the hardware device. An instruction includes request to access a physical address. The hardware device compares the domain identifier of the instruction with the permissions. If the permissions allow the domain identifier to access the physical address, then access to the resource at the physical address is allowed. Access is otherwise blocked.

Abstract translation: 方法和装置在处理器核心中配置可信域和多个隔离域。 每个隔离域都被分配一个唯一的域标识符。 一个或多个资源与每个孤立的域相关联。 这些关联被存储为访问资源的物理地址的权限。 要由硬件设备执行的代码被分配给一个隔离的域。 分配的隔离域的域标识符写入硬件设备。 当硬件设备执行代码时，每个指令都用写入硬件设备的域标识符进行逻辑标记。 指令包括访问物理地址的请求。 硬件设备将指令的域标识与权限进行比较。 如果权限允许域标识符访问物理地址，则允许访问物理地址上的资源。 访问被阻止。

公开(公告)号：US08392745B2

公开(公告)日：2013-03-05

申请号：US12767226

申请日：2010-04-26

Applicant: Greg Goodemote ,  Khan Kibria ,  Mark N. Fullerton ,  Niray P. Dagli ,  Liang Deng ,  Sam Liu

Inventor： Greg Goodemote ,  Khan Kibria ,  Mark N. Fullerton ,  Niray P. Dagli ,  Liang Deng ,  Sam Liu

IPC: G06F1/00

CPC classification number: G06F1/26 ,  G06F1/06 ,  G06F1/08

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The hub module includes a clock control circuit, coupled to the plurality of hub interfaces, that selectively supplies a plurality of clock signals to the plurality of spoke modules by receiving a clock request signal from a corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces, generating at least one of the plurality of clock signals in response to the clock request signal; and sending the at least one of the plurality of clock signals to the corresponding one of the plurality of spoke modules via the signal interface of the corresponding one of the plurality of hub interfaces.

Abstract translation: 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 集线器模块包括耦合到多个集线器接口的时钟控制电路，其通过经由信号从多个辐条模块中的相应一个接收时钟请求信号来选择性地将多个时钟信号提供给多个辐条模块 接口，响应于时钟请求信号产生多个时钟信号中的至少一个; 以及经由所述多个集线器接口中相应一个的所述信号接口将所述多个时钟信号中的至少一个发送到所述多个辐条模块中的对应的一个。

公开(公告)号：US08386688B2

公开(公告)日：2013-02-26

申请号：US12770690

申请日：2010-04-29

Applicant: Mark N. Fullerton ,  Robert Morris ,  Lance Flake ,  Lawrence J. Madar, III ,  Sam Liu ,  Chaoyang Zhao ,  Vinay Bhasin ,  Joyjit Nath ,  Bhupesh Kharwa ,  Claude G. Hayek

Inventor： Mark N. Fullerton ,  Robert Morris ,  Lance Flake ,  Lawrence J. Madar, III ,  Sam Liu ,  Chaoyang Zhao ,  Vinay Bhasin ,  Joyjit Nath ,  Bhupesh Kharwa ,  Claude G. Hayek

IPC: G06F13/36

CPC classification number: G06F13/28 ,  G06F1/10 ,  G06F1/26 ,  G06F13/4027 ,  G06F2213/0038 ,  Y02D30/34

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. The plurality of hub interfaces provide a plurality of signal interfaces between the hub module and each of the plurality of spoke modules, wherein each of the plurality of signal interfaces is isolated from each of the other signal interfaces of the plurality of signals interface, and wherein each of the plurality of signal interfaces operates in accordance with a common signaling format.

公开(公告)号：US20120159018A1

公开(公告)日：2012-06-21

申请号：US13406007

申请日：2012-02-27

Applicant: Ofer Bar-Shalom ,  Mark N. Fullerton ,  Alon Tsafrir

Inventor： Ofer Bar-Shalom ,  Mark N. Fullerton ,  Alon Tsafrir

IPC: G06F13/24

CPC classification number: G06F13/28

Abstract: A method for operating a host device includes comparing a predetermined response of a peripheral device to a response token received from the peripheral device. The predetermined response and the response token are generated based on a first command transmitted from the host device to the peripheral device. The method further includes controlling a transfer of first data from a first memory to a peripheral control module based on the comparison between the predetermined response and the response token without interrupting a host control module, and selectively passing interrupts to the host control module when the predetermined response does not match the response token.

Abstract translation: 用于操作主机设备的方法包括将外围设备的预定响应与从外围设备接收的响应令牌进行比较。 基于从主机设备向外围设备发送的第一命令来生成预定响应和响应令牌。 该方法还包括基于预定响应和响应令牌之间的比较来控制从第一存储器到外围控制模块的传输，而不中断主机控制模块，以及当预定的时间间隔时间选择性地将中断传送到主机控制模块 响应与响应令牌不匹配。

公开(公告)号：US20110264930A1

公开(公告)日：2011-10-27

申请号：US12767208

申请日：2010-04-26

Applicant: Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

Inventor： Lawrence J. Madar, III ,  Mark N. Fullerton ,  Bhupesh Kharwa

IPC: G06F12/06 ,  G06F1/04 ,  G06F1/26

CPC classification number: G06F9/00 ,  G06F1/06 ,  G06F1/189 ,  G06F1/26 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/3296 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D50/20

Abstract: A modular integrated circuit includes a hub module that is coupled to a plurality of spoke modules via a plurality of hub interfaces. A memory module stores hub software and hub data and configuration data. The hub software operates in accordance with a memory map that includes a plurality of first reserved blocks corresponding to memory reserved for the plurality of spoke modules, and at least one second reserved block corresponding to memory reserved for at least one optional spoke module. The plurality of first reserved blocks are activated based on the configuration data and the at least one second reserved block is deactivated based on the configuration data.

Abstract translation: 模块化集成电路包括经由多个集线器接口耦合到多个辐条模块的集线器模块。 存储器模块存储集线器软件和集线器数据和配置数据。 集线器软件根据存储器映射进行操作，存储器映射包括与为多个辐条模块保留的存储器相对应的多个第一保留块，以及对应于至少一个可选辐条模块保留的存储器的至少一个第二保留块。 基于配置数据激活多个第一保留块，并且基于配置数据停用至少一个第二保留块。

公开(公告)号：US20080288748A1

公开(公告)日：2008-11-20

申请号：US12215760

申请日：2008-06-30

Applicant: Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

Inventor： Sehat Sutardja ,  Hong-Yi Chen ,  Premanand Sakarda ,  Mark N. Fullerton ,  Jay Heeb

IPC: G06F15/80 ,  G06F9/00

CPC classification number: G06F1/3293 ,  G06F1/3203 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/3017 ,  G06F9/30174 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3885 ,  G06F9/461 ,  G06F9/4856 ,  G06F9/4893 ,  Y02D10/122 ,  Y02D10/171 ,  Y02D10/24 ,  Y02D10/32 ,  Y02D50/20

Abstract: A core switching system includes a mode switching module that receives a switch signal to switch operation between a first mode and a second mode. During the first mode, instructions associated with applications are executed by a first asymmetric core, and a second asymmetric core is inactive. During the second mode, the instructions are executed by the second asymmetric core, and the first asymmetric core is inactive. A core activation module stops processing of the applications by the first asymmetric core after interrupts are disabled. A state transfer module transfers a state of the first asymmetric core to the second asymmetric core. The core activation module allows the second asymmetric core to resume execution of the instructions and the interrupts are enabled.

Abstract translation: 核心交换系统包括模式切换模块，其接收切换信号以在第一模式和第二模式之间切换操作。 在第一模式期间，与应用相关联的指令由第一不对称核执行，而第二非对称核是不活动的。 在第二模式期间，指令由第二非对称核执行，第一非对称核是不活动的。 核心激活模块在禁止中断之后停止第一个非对称核心处理应用程序。 状态转移模块将第一不对称核的状态转移到第二不对称核。 核心激活模块允许第二非对称核继续执行指令，中断被使能。