公开(公告)号：US20110117741A1

公开(公告)日：2011-05-19

申请号：US12926123

申请日：2010-10-27

Applicant: Tomohiro Okamura ,  Masao Okihara

Inventor： Tomohiro Okamura ,  Masao Okihara

IPC: H01L21/302

CPC classification number: H01L21/76256

Abstract: There is provided a method of fabricating an SOI wafer, the method including: a) preparing a bonded SOI substrate that has a buried oxide layer and an SOI layer formed in this sequence on a circular plate shaped support, and at a peripheral edge portion of the support substrate, has a silicon island region in which the SOI layer is not well formed with scattered defective silicon layer; b) etching a silicon island region defective silicon layer to remove the defective silicon layer scattered in the silicon island region by dry etching; and c) etching a silicon island region buried oxide layer to remove the buried oxide layer in the silicon island region by wet etching.

Abstract translation: 提供一种制造SOI晶片的方法，该方法包括：a）制备具有掩埋氧化物层和以此顺序形成的SOI层的键合SOI衬底在圆形板状支撑体上，并在其周边部分 支撑基板具有硅层，其中SOI层不是很好地形成有散射的有缺陷的硅层; b）蚀刻硅岛区域不良硅层，以通过干蚀刻去除在硅岛区域中散布的有缺陷的硅层; 以及c）蚀刻硅岛区掩埋氧化物层，以通过湿蚀刻去除硅岛区域中的掩埋氧化物层。

公开(公告)号：US20110101458A1

公开(公告)日：2011-05-05

申请号：US12929282

申请日：2011-01-12

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L27/0266 ,  H01L29/78

Abstract: An SOI type semiconductor device having a silicon substrate and a buried oxide layer formed on the silicon substrate includes an internal circuit formed in a first region having at least one FD type transistor having a SOI structure, the internal circuit performing a function of the semiconductor device and a protection circuit formed in a second region having at least one PD type transistor having a SOI structure, the protection circuit protecting the internal circuit from electro static damage.

Abstract translation: 具有在硅衬底上形成的硅衬底和掩埋氧化层的SOI型半导体器件包括形成在具有SOI结构的至少一个FD型晶体管的第一区域中的内部电路，该内部电路执行半导体器件的功能 以及形成在具有至少一个具有SOI结构的PD型晶体管的第二区域中的保护电路，所述保护电路保护所述内部电路免受静电损坏。

公开(公告)号：US07300851B2

公开(公告)日：2007-11-27

申请号：US11331258

申请日：2006-01-13

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/331

CPC classification number: H01L29/78609 ,  H01L21/76281

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an 501 substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional, doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract translation: 绝缘体上硅（SOI）器件的制造工艺包括在501衬底中限定有源区，用给定导电类型的杂质掺杂整个有源区，掩蔽有源区的主要部分，并掺杂 有源区的外围部分至少两次，其中杂质具有相同的导电类型，优选地每次使用不同的掺杂参数。 附加的掺杂在有源区域的外围部分中产生通道停止，抵消在有源区域的外围部分中晶体管阈值电压降低的倾向，从而减轻或消除在晶体管中经常发现的不希望的次阈值突峰 例如，完全耗尽的SOI器件的工作特性。

公开(公告)号：US07112501B2

公开(公告)日：2006-09-26

申请号：US10687839

申请日：2003-10-20

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/331

CPC classification number: H01L29/78609 ,  H01L21/76281

Abstract: A fabrication process for a silicon-on-insulator (SOI) device includes defining an active region in an SOI substrate, doping the entire active region with an impurity of a given conductive type, masking a main part of the active region, and doping the peripheral parts of the active region at least two additional times with an impurity of the same conductive type, preferably using different doping parameters each time. The additional doping creates a channel stop in the peripheral parts of the active region, counteracting the tendency of the transistor threshold voltage to be lowered in the peripheral parts of the active region, thereby mitigating or eliminating the unwanted subthreshold hump often found in the transistor operating characteristics of, for example, fully depleted SOI devices.

Abstract translation: 绝缘体上硅（SOI）器件的制造方法包括在SOI衬底中限定有源区，用给定导电类型的杂质掺杂整个有源区，掩蔽有源区的主要部分，并掺杂 有源区的外围部分至少两次，其中杂质具有相同的导电类型，优选地每次使用不同的掺杂参数。 附加掺杂在有源区域的外围部分中产生通道阻挡，抵消在有源区域的外围部分中晶体管阈值电压降低的趋势，从而减轻或消除在晶体管工作中经常发现的不希望的阈值突峰 特征，例如，完全耗尽的SOI器件。

公开(公告)号：US5892225A

公开(公告)日：1999-04-06

申请号：US766613

申请日：1996-12-13

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: G01N1/28 ,  G01N1/32 ,  G01R31/307 ,  H01J37/295 ,  H01J37/26

CPC classification number: G01R31/307 ,  G01N1/32

Abstract: A plan-view sample of an integrated circuit is prepared for transmission electron microscopy by marking a faulty circuit element, lapping the upper surface of the sample to a mirror finish, lapping the lower surface to reduce the thickness of the entire sample, and further processing the lower surface by lapping or dimpling, combined with ion milling as necessary, to thin the sample in the vicinity of the fault. A sample prepared in this way affords a wide view, and can be tilted at large angles. A known thickness of a particular type of layer in the sample can be left by holding the sample at a predetermined angle while the sample is lapped.

Abstract translation: 通过标记故障电路元件，将样品的上表面研磨成镜面，制备集成电路的平面图样品用于透射电子显微镜，研磨下表面以减小整个样品的厚度，并进一步处理 通过研磨或凹坑的下表面，结合根据需要的离子铣削，使样品在故障附近变薄。 以这种方式制备的样品可以获得宽视角，并且可以以大的角度倾斜。 通过在样品被研磨的同时将样品保持在预定角度，可以留下样品中特定类型的层的已知厚度。

公开(公告)号：US20120193714A1

公开(公告)日：2012-08-02

申请号：US13362093

申请日：2012-01-31

Applicant: MASAO OKIHARA

Inventor： MASAO OKIHARA

IPC: H01L29/772 ,  H01L21/762 ,  H01L21/336

CPC classification number: H01L29/78603 ,  H01L21/76254 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/66772 ,  H01L29/785 ,  H01L29/78621

Abstract: Disclosed is an SOI substrate which includes a semiconductor base; a semiconductor layer formed over the semiconductor base; and a buried insulating film which is disposed between the semiconductor base and the semiconductor layer, so as to electrically isolate the semiconductor layer from the semiconductor base, where the buried insulating film contains a nitride film.

Abstract translation: 公开了一种SOI衬底，其包括半导体基底; 形成在半导体基底上的半导体层; 以及掩埋绝缘膜，其设置在半导体基底和半导体层之间，以将半导体层与半导体基底电隔离，其中埋入绝缘膜包含氮化物膜。

公开(公告)号：US08071415B2

公开(公告)日：2011-12-06

申请号：US12659601

申请日：2010-03-15

Applicant: Tomohiro Okamura ,  Masao Okihara

Inventor： Tomohiro Okamura ,  Masao Okihara

IPC: H01L21/00

CPC classification number: H01L27/14 ,  H01L27/144

Abstract: There is provided a method of fabricating a semiconductor device having plural light receiving elements, and having an amplifying element, the method including: a) forming an active region on the semiconductor substrate for configuring the amplifying element; b) forming a light receiving element region on the semiconductor substrate for forming the plural light receiving elements, with the active region acting as a reference for positioning; c) implanting an impurity into the light receiving element region; d) repeating the process b) and the process c) a number of times that equals a number of diffusion layers in the light receiving element region; e) after implanting the impurity, performing a drive-in process to carry out drive in of the semiconductor substrate; and f) the process e), forming an amplifying element forming process by implanting an impurity in the active region.

Abstract translation: 提供一种制造具有多个光接收元件并具有放大元件的半导体器件的方法，该方法包括：a）在半导体衬底上形成用于配置放大元件的有源区; b）在所述半导体衬底上形成用于形成所述多个光接收元件的受光元件区域，所述有源区域用作定位的基准; c）将杂质注入光接收元件区域; d）重复步骤b）和过程c）等于光接收元件区域中的多个扩散层的次数; e）在注入杂质之后，执行驱动工艺以进行半导体衬底的驱动; 和f）工艺e），通过在有源区中注入杂质形成放大元件形成工艺。

公开(公告)号：US07985638B2

公开(公告)日：2011-07-26

申请号：US12487952

申请日：2009-06-19

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L21/336

CPC classification number: H01L29/42384 ,  H01L21/28052 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/4975 ,  H01L29/665 ,  H01L29/6653

Abstract: A semiconductor device manufacturing method which sequentially forms a gate oxide film and gate electrode material over a semiconductor layer of an SOI substrate and patterns the material into gate electrodes. The method further comprises the steps of forming sidewalls made of an insulator to cover side surfaces of the gate electrode; ion-implanting into the semiconductor layer on both sides of the gate electrode to form drain/source regions; partially etching the sidewalls to expose upper parts of the side surfaces of the gate electrode; depositing a metal film to cover the tops of the drain/source regions and of the gate electrode and the exposed upper parts of the side surfaces of the gate electrode; and performing heat treatment on the SOI substrate to form silicide layers respectively in the surfaces of the gate electrode and of the drain/source regions.

Abstract translation: 一种在SOI衬底的半导体层上依次形成栅极氧化膜和栅电极的半导体器件制造方法，并将该材料图案化成栅电极。 该方法还包括以下步骤：形成由绝缘体制成的侧壁以覆盖栅电极的侧表面; 离子注入到栅极两侧的半导体层中以形成漏极/源极区; 部分蚀刻侧壁以暴露栅电极的侧表面的上部; 沉积金属膜以覆盖漏极/源极区域以及栅电极的顶部和栅电极的侧表面的暴露的上部; 对SOI衬底进行热处理，分别在栅极电极和漏极/源极区域的表面形成硅化物层。

公开(公告)号：US20100248410A1

公开(公告)日：2010-09-30

申请号：US12659601

申请日：2010-03-15

Applicant: Tomohiro Okamura ,  Masao Okihara

Inventor： Tomohiro Okamura ,  Masao Okihara

IPC: H01L31/18

CPC classification number: H01L27/14 ,  H01L27/144

Abstract: There is provided a method of fabricating a semiconductor device having plural light receiving elements, and having an amplifying element, the method including: a) forming an active region on the semiconductor substrate for configuring the amplifying element; b) forming a light receiving element region on the semiconductor substrate for forming the plural light receiving elements, with the active region acting as a reference for positioning; c) implanting an impurity into the light receiving element region; d) repeating the process b) and the process c) a number of times that equals a number of diffusion layers in the light receiving element region; e) after implanting the impurity, performing a drive-in process to carry out drive in of the semiconductor substrate; and f) the process e), forming an amplifying element forming process by implanting an impurity in the active region.

Abstract translation: 提供一种制造具有多个光接收元件并具有放大元件的半导体器件的方法，该方法包括：a）在半导体衬底上形成用于配置放大元件的有源区; b）在所述半导体衬底上形成用于形成所述多个光接收元件的受光元件区域，所述有源区域用作定位的基准; c）将杂质注入光接收元件区域; d）重复步骤b）和过程c）等于光接收元件区域中的多个扩散层的次数; e）在注入杂质之后，执行驱动工艺以进行半导体衬底的驱动; 和f）工艺e），通过在有源区中注入杂质形成放大元件形成工艺。

公开(公告)号：US20100244135A1

公开(公告)日：2010-09-30

申请号：US12659947

申请日：2010-03-25

Applicant: Masao Okihara

Inventor： Masao Okihara

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/823814 ,  H01L21/823878

Abstract: In a semiconductor device of a silicon on insulator (SOI) structure having uniform transistor properties, a first distance between a gate electrode forming position of an N type transistor and an end of a P type semiconductor region is greater than a second distance between a gate electrode forming position of the P type transistor and an edge of the N type semiconductor region.

Abstract translation: 在具有均匀晶体管特性的绝缘体上硅（SOI）结构的半导体器件中，N型晶体管的栅电极形成位置与P型半导体区域的端部之间的第一距离大于栅极之间的第二距离 P型晶体管的电极形成位置和N型半导体区域的边缘。