公开(公告)号：US08351276B2

公开(公告)日：2013-01-08

申请号：US12835309

申请日：2010-07-13

Applicant: Jon S. Choy ,  Chen He ,  Michael A. Sadd

Inventor： Jon S. Choy ,  Chen He ,  Michael A. Sadd

IPC: G11C11/34

CPC classification number: G11C16/3468 ,  G11C16/0483 ,  G11C16/16

Abstract: A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.

Abstract translation: 一种方法包括擦除位并识别被擦除过度擦除的位。 已经被擦除的位的第一个子集是软编程的。 测量第一个子集的软编程的结果。 选择基于来自软编程的结果的多个可能的电压条件的初始电压状态。 已经被擦除的位的第二个子集是软编程的。 软编程将初始电压条件应用于位的第二子集中的位。 第二子集包括当选择步骤发生时仍然被擦除的比特。 结果是，用于第二子集的软编程可以在更优化的点开始，以便快速实现所需的软编程以使所有位都处于所需的擦除条件。

公开(公告)号：US20120113714A1

公开(公告)日：2012-05-10

申请号：US12942285

申请日：2010-11-09

Applicant: JON S. CHOY ,  Chen He ,  Michael A. Sadd

Inventor： JON S. CHOY ,  Chen He ,  Michael A. Sadd

IPC: G11C16/12

CPC classification number: G11C16/10 ,  G11C11/5628

Abstract: A method is provided for programming a multi-state flash memory having a plurality of memory cells. A first programming pulse is provided to the flash array; determining a threshold voltage distribution for the plurality of memory cells after providing the first programming pulse. The plurality of memory cells is categorized into at least two bins based on a threshold voltage of each memory cell of the plurality of memory cells. A first voltage is selected for a second programming pulse for programming a first bin of memory cells of the at least two bins, the first voltage based on both a threshold voltage of the first bin and a first target threshold voltage. A second voltage is selected for a third programming pulse for programming a second bin of memory cells of the at least two bins, the second voltage based on both the threshold voltage of the second bin and on a second target threshold voltage.

Abstract translation: 提供了一种用于对具有多个存储单元的多状态闪存进行编程的方法。 向闪存阵列提供第一编程脉冲; 在提供所述第一编程脉冲之后，确定所述多个存储器单元的阈值电压分布。 基于多个存储器单元中的每个存储器单元的阈值电压将多个存储单元分成至少两个箱。 为第二编程脉冲选择第一电压，用于对所述至少两个存储体的存储器单元的第一仓进行编程，所述第一电压基于所述第一仓的阈值电压和第一目标阈值电压。 为第三编程脉冲选择第二电压，用于根据第二仓的阈值电压和第二目标阈值电压来编程至少两个存储体的第二存储单元的第二存储单元。

公开(公告)号：US20120014179A1

公开(公告)日：2012-01-19

申请号：US12835309

申请日：2010-07-13

Applicant: Jon S. Choy ,  Chen He ,  Michael A. Sadd

Inventor： Jon S. Choy ,  Chen He ,  Michael A. Sadd

IPC: G11C16/04

CPC classification number: G11C16/3468 ,  G11C16/0483 ,  G11C16/16

Abstract: A method includes erasing bits and identifying bits that have been over-erased by the erasing. A first subset of the bits that have been over-erased are soft programmed. The results of soft programming the first subset of bits is measured. An initial voltage condition from a plurality of possible voltage conditions based on the results from soft programming the first subset of bits is selected. A second subset of bits that have been over-erased are soft programmed. The soft programming applies the initial voltage condition to the bits in the second subset of bits. The second subset comprises bits that are still over-erased when the step of selecting occurs. The result is that the soft programming for the second subset may begin at a more optimum point for quickly achieving the needed soft programming to bring all of the bits within the desired erase condition.

Abstract translation: 一种方法包括擦除位并识别被擦除过度擦除的位。 已经被擦除的位的第一个子集是软编程的。 测量第一个子集的软编程的结果。 选择基于来自软编程的结果的多个可能的电压条件的初始电压状态。 已经被擦除的位的第二个子集是软编程的。 软编程将初始电压条件应用于位的第二子集中的位。 第二子集包括当选择步骤发生时仍然被擦除的比特。 结果是，用于第二子集的软编程可以在更优化的点开始，以便快速实现所需的软编程以使所有位都处于所需的擦除条件。

公开(公告)号：US07619275B2

公开(公告)日：2009-11-17

申请号：US11188935

申请日：2005-07-25

Applicant: Michael A. Sadd ,  Ko-Min Chang ,  Gowrishankar L. Chindalore ,  Cheong M. Hong ,  Craig T. Swift

Inventor： Michael A. Sadd ,  Ko-Min Chang ,  Gowrishankar L. Chindalore ,  Cheong M. Hong ,  Craig T. Swift

IPC: H01L21/336

CPC classification number: H01L27/115 ,  B82Y10/00 ,  G11C16/0475 ,  H01L21/7624 ,  H01L27/11519 ,  H01L27/11556 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42336

Abstract: A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.

Abstract translation: 用于形成电子器件的方法可以包括在衬底内形成沟槽，其中沟槽包括壁和底部。 该方法还可以包括形成位于沟槽内的不连续存储元件的一部分，以及在形成不连续存储元件之后在沟槽内形成第一栅电极。 至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。 该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。

公开(公告)号：US07563681B2

公开(公告)日：2009-07-21

申请号：US11341973

申请日：2006-01-27

Applicant: Craig T. Swift ,  Thuy B. Dao ,  Michael A. Sadd

Inventor： Craig T. Swift ,  Thuy B. Dao ,  Michael A. Sadd

IPC: H01L21/8234

CPC classification number: H01L21/28282 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/76251 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/78648 ,  H01L29/7887 ,  H01L29/7923

Abstract: A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.

Abstract translation: 制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体结构，第一存储层和栅极材料层，其中所述第一存储 层位于半导体结构和栅极材料层之间并且比半导体结构更靠近第二晶片的第一侧。 该方法还包括将第二晶片的第一侧接合到第一晶片并且在结合之后解除半导体结构的第一部分以留下半导体结构层。 该方法还包括在半导体结构的层上形成第二存储层，并在第二存储层上形成顶栅。

公开(公告)号：US20090166712A1

公开(公告)日：2009-07-02

申请号：US12397849

申请日：2009-03-04

Applicant: Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

Inventor： Ramachandran Muralidhar ,  Rajesh A. Rao ,  Michael A. Sadd ,  Bruce E. White

IPC: H01L29/78

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/7881 ,  Y10S977/773

Abstract: A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.

Abstract translation: 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。

公开(公告)号：US06444545B1

公开(公告)日：2002-09-03

申请号：US09740249

申请日：2000-12-19

Applicant: Michael A. Sadd ,  Sucharita Madhukar ,  Frank Kelsey Baker

Inventor： Michael A. Sadd ,  Sucharita Madhukar ,  Frank Kelsey Baker

IPC: H01L2120

CPC classification number: H01L29/42332 ,  B82Y10/00 ,  H01L21/28273 ,  H01L21/28282

Abstract: A semiconductor device structure for storing charge has a silicon nitride layer, in which a plurality of nanoclusters are sandwiched between oxide layers. The nanoclusters and the silicon nitride make up a storage region, which is particularly useful in non-volatile memories. The nanoclusters provide a repository for holes or electrons that jump from trap to trap in the silicon nitride when the silicon nitride is heated. This results in much of the charge, which would normally leak off from the silicon nitride at high temperatures, remaining in the storage region due to trapping in the nanoclusters. The silicon nitride layer with nanoclusters therein is formed by depositing a silicon nitride layer, then nanoclusters, and then another silicon nitride layer or by depositing a silicon-rich silicon nitride layer and subsequent heating to cause it to transform to a regular silicon nitride layer with silicon nanoclusters therein.

Abstract translation: 用于存储电荷的半导体器件结构具有氮化硅层，其中多个纳米团簇夹在氧化物层之间。 纳米团簇和氮化硅组成存储区域，这在非易失性存储器中特别有用。 当氮化硅被加热时，纳米团簇提供了在氮化硅中从阱陷阱陷阱的空穴或电子库。 这导致大量的电荷，其通常在高温下从氮化硅泄漏出来，由于在纳米团簇中的捕获而残留在存储区域中。 其中具有纳米团簇的氮化硅层通过沉积氮化硅层，然后沉积纳米团簇，然后沉积另一个氮化硅层或通过沉积富硅氮化硅层并随后加热使其转变成规则的氮化硅层而形成， 硅纳米团簇。