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公开(公告)号：US07582929B2
公开(公告)日：2009-09-01
申请号：US11188999
申请日：2005-07-25
IPC分类号： H01L29/94
CPC分类号： H01L29/7887 , B82Y10/00 , H01L21/28273 , H01L27/115 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336 , H01L29/66825
摘要： An electronic device can include discontinuous storage elements that lie within a trench. In one embodiment, the electronic device can include a substrate having a trench that includes a wall and a bottom. The electronic device can also include a portion of discontinuous storage elements that lie within the trench. The electronic device can also include a first gate electrode, wherein at least one discontinuous storage element lies along the wall of the trench at an elevation between and upper surface of the first gate electrode and a primary surface of the substrate. The electronic device can also include a second gate electrode overlying the first gate electrode and the primary surface of the substrate. In another embodiment, a conductive line can be electrically connected to one or more rows or columns of memory cells, and another conductive line can be more rows or more columns of memory cells.
摘要翻译： 电子设备可以包括位于沟槽内的不连续存储元件。 在一个实施例中，电子设备可以包括具有包括壁和底部的沟槽的衬底。 电子设备还可以包括位于沟槽内的不连续存储元件的一部分。 电子器件还可以包括第一栅电极，其中至少一个不连续存储元件沿着沟槽的壁位于第一栅电极的上表面和衬底的主表面之间的高度处。 电子器件还可以包括覆盖在第一栅电极和衬底的主表面上的第二栅电极。 在另一个实施例中，导线可以电连接到一个或多个存储单元的行或列，而另一个导线可以是更多行或更多列的存储单元。
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2.发明授权Process for forming an electronic device including discontinuous storage elements 失效用于形成包括不连续存储元件的电子设备的方法公开(公告)号：US07619275B2
公开(公告)日：2009-11-17
申请号：US11188935
申请日：2005-07-25
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , B82Y10/00 , G11C16/0475 , H01L21/7624 , H01L27/11519 , H01L27/11556 , H01L29/42328 , H01L29/42332 , H01L29/42336
摘要： A process for forming an electronic device can include forming a trench within a substrate, wherein the trench includes a wall and a bottom. The process can also include including forming a portion of discontinuous storage elements that lie within the trench, and forming a first gate electrode within the trench after forming the discontinuous storage elements. At least one discontinuous storage element lies along the wall of the trench at an elevation between an upper surface of the first gate electrode and a primary surface of the substrate. The process can also include forming a second gate electrode overlying the first gate electrode and the primary surface of the substrate.
摘要翻译： 用于形成电子器件的方法可以包括在衬底内形成沟槽，其中沟槽包括壁和底部。 该方法还可以包括形成位于沟槽内的不连续存储元件的一部分，以及在形成不连续存储元件之后在沟槽内形成第一栅电极。 至少一个不连续的存储元件位于第一栅电极的上表面和衬底的主表面之间的海拔处的沟槽的壁处。 该工艺还可以包括形成覆盖在第一栅电极和衬底的主表面上的第二栅电极。
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3.发明授权Back-gated semiconductor device with a storage layer and methods for forming thereof 有权具有存储层的后门控半导体器件及其形成方法公开(公告)号：US07679125B2
公开(公告)日：2010-03-16
申请号：US11300077
申请日：2005-12-14
IPC分类号： H01L29/76
CPC分类号： H01L21/28273 , B82Y10/00 , H01L21/28282 , H01L21/84 , H01L27/1203 , H01L29/66825 , H01L29/66833 , H01L29/7887 , H01L29/7923
摘要： A method of making a semiconductor device includes providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor substrate, a storage layer, and a layer of gate material. The storage layer may be located between the semiconductor structure and the layer of the gate material and the storage layer may be located closer to the first side of the second wafer than the semiconductor structure. The method further includes boding the first side of the second wafer to the first wafer. The method further includes removing a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a transistor having a channel region, wherein at least a portion of the channel region is formed from the layer of the semiconductor structure.
摘要翻译： 制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体衬底，存储层和栅极材料层。 存储层可以位于半导体结构和栅极材料层之间，并且存储层可以比半导体结构更靠近第二晶片的第一侧。 该方法还包括将第二晶片的第一侧布置到第一晶片。 该方法还包括去除半导体结构的第一部分以在结合之后留下半导体结构层。 该方法还包括形成具有沟道区的晶体管，其中沟道区的至少一部分由半导体结构的层形成。
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公开(公告)号：US07622349B2
公开(公告)日：2009-11-24
申请号：US11302937
申请日：2005-12-14
IPC分类号： H01L21/8239 , H01L21/28
CPC分类号： H01L29/792 , H01L27/115 , H01L27/11521 , H01L29/42324 , H01L29/4234 , H01L29/7881
摘要： A method is provided which includes forming a first gate overlying a major surface of an electronic device substrate and forming a second gate overlying and spaced apart from the first gate. The method further includes forming a charge storage structure horizontally adjacent to, and continuous along, the first gate and the second gate, wherein a major surface of the charge storage structure is substantially vertical to the major surface of the substrate.
摘要翻译： 提供了一种方法，其包括形成覆盖在电子器件基板的主表面上的第一栅极并且形成覆盖并与第一栅极间隔开的第二栅极。 该方法还包括形成电荷存储结构，该电荷存储结构沿着第一栅极和第二栅极水平相邻并连续地延伸，其中电荷存储结构的主表面基本上垂直于衬底的主表面。
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公开(公告)号：US06847548B2
公开(公告)日：2005-01-25
申请号：US10601256
申请日：2003-06-20
申请人： Craig T. Swift , Michael A. Sadd
发明人： Craig T. Swift , Michael A. Sadd
CPC分类号： G11C16/0491 , G11C16/0475
摘要： A memory has an array made up of transistors that have two charge storage regions between the channel and control gate. Each bit is made up of two charge storage regions that are from different transistors. A bit is written by first erasing all of the storage locations and then writing one of the charge storage locations that make up the bit. A pair of charge storage locations, one erased and the other programmed, is identified for each bit. The logic state of the bit is read by comparing the charge stored in the two charge storage locations that make up the bit. This comparison is achieved by generating signals representative of the charge present in the two charge storage locations. These signals are then coupled to a sense amplifier that functions as a comparator. This avoids many problems that accompany comparisons to a fixed reference.
摘要翻译： 存储器具有由在通道和控制栅极之间具有两个电荷存储区域的晶体管组成的阵列。 每个位由来自不同晶体管的两个电荷存储区组成。 首先擦除所有存储位置，然后写入构成该位的电荷存储位置之一，写入一位。 每一位识别一对电荷存储单元，一个被擦除，另一个编程。 通过比较存储在构成该位的两个电荷存储位置中的电荷来读取该位的逻辑状态。 该比较通过产生表示两个电荷存储位置中存在的电荷的信号来实现。 这些信号然后被耦合到用作比较器的读出放大器。 这避免了许多与固定参考比较的问题。
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公开(公告)号：US07160775B2
公开(公告)日：2007-01-09
申请号：US10912825
申请日：2004-08-06
申请人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
发明人： Erwin J. Prinz , Ramachandran Muralidhar , Rajesh A. Rao , Michael A. Sadd , Robert F. Steimle , Craig T. Swift , Bruce E. White
IPC分类号： H01L21/336
CPC分类号： B82Y10/00 , G11C16/0475 , G11C16/14 , G11C2216/06 , H01L21/28273 , H01L21/28282 , H01L29/42332
摘要： In one embodiment, a method for discharging a semiconductor device includes providing a semiconductor substrate, forming a hole blocking dielectric layer over the semiconductor substrate, forming nanoclusters over the hole blocking dielectric layer, forming a charge trapping layer over the nanoclusters, and applying an electric field to the nanoclusters to discharge the semiconductor device. Applying the electric field may occur while applying ultraviolet (UV) light. In one embodiment, the hole blocking dielectric layer comprises forming the hole blocking dielectric layer having a thickness greater than approximately 50 Angstroms.
摘要翻译： 在一个实施例中，一种用于放电半导体器件的方法包括提供半导体衬底，在半导体衬底上形成空穴阻挡电介质层，在空穴阻挡介电层上形成纳米团簇，在纳米团簇上形成电荷俘获层，并施加电 场到纳米团簇放电半导体器件。 施加紫外线（UV）光时可能会发生电场。 在一个实施例中，空穴阻挡介电层包括形成厚度大于约50埃的空穴阻挡介电层。
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公开(公告)号：US07563681B2
公开(公告)日：2009-07-21
申请号：US11341973
申请日：2006-01-27
申请人： Craig T. Swift , Thuy B. Dao , Michael A. Sadd
发明人： Craig T. Swift , Thuy B. Dao , Michael A. Sadd
IPC分类号： H01L21/8234
CPC分类号： H01L21/28282 , B82Y10/00 , H01L21/28273 , H01L21/76251 , H01L29/66825 , H01L29/66833 , H01L29/78648 , H01L29/7887 , H01L29/7923
摘要： A method for making a semiconductor device comprises providing a first wafer and providing a second wafer having a first side and a second side, the second wafer including a semiconductor structure, a first storage layer, and a layer of gate material, wherein the first storage layer is located between the semiconductor structure and the layer of gate material and closer to the first side of the second wafer than the semiconductor structure. The method further includes bonding the first side of the second wafer to the first wafer and cleaving away a first portion of the semiconductor structure to leave a layer of the semiconductor structure after the bonding. The method further includes forming a second storage layer over the layer of the semiconductor structure and forming a top gate over the second storage layer.
摘要翻译： 制造半导体器件的方法包括提供第一晶片并提供具有第一侧和第二侧的第二晶片，所述第二晶片包括半导体结构，第一存储层和栅极材料层，其中所述第一存储 层位于半导体结构和栅极材料层之间并且比半导体结构更靠近第二晶片的第一侧。 该方法还包括将第二晶片的第一侧接合到第一晶片并且在结合之后解除半导体结构的第一部分以留下半导体结构层。 该方法还包括在半导体结构的层上形成第二存储层，并在第二存储层上形成顶栅。
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8.发明申请公开(公告)号：US20120241909A1
公开(公告)日：2012-09-27
申请号：US13070049
申请日：2011-03-23
摘要： A process and device structure is provided for increasing capacitance density of a capacitor structure. A sandwich capacitor is provided in which a bottom silicon-containing conductor plate is formed with holes or cavities, upon which an oxide layer and a top silicon-containing layer conductor is formed. The holes or cavities provide additional capacitive area, thereby increasing capacitance per footprint area of the capacitor structure. The holes can form, for example, a line structure or a waffle-like structure in the bottom conductor plate. Etching techniques used to form the holes in the bottom conductor plate can also result in side wall tapering of the holes, thereby increasing the surface area of the silicon-containing layer defined by the holes. In addition, depth of holes can be adjusted through timed etching to further adjust capacitive area.
摘要翻译： 提供了一种用于增加电容器结构的电容密度的工艺和器件结构。 提供一种夹层电容器，其中底部含硅导电板形成有孔或空腔，在其上形成氧化物层和顶部含硅层导体。 孔或腔提供附加的电容区域，从而增加电容器结构的每个覆盖区域的电容。 孔可以形成例如底部导体板中的线结构或华夫饼状结构。 用于在底部导体板中形成孔的蚀刻技术还可导致孔的侧壁渐缩，从而增加由孔限定的含硅层的表面积。 此外，可以通过定时蚀刻来调整孔的深度，以进一步调整电容面积。
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公开(公告)号：US07800164B2
公开(公告)日：2010-09-21
申请号：US12397849
申请日：2009-03-04
IPC分类号： H01L29/792
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513 , H01L29/7881 , Y10S977/773
摘要： A method of forming a semiconductor device includes forming a first dielectric layer over a semiconductor substrate, forming a plurality of discrete storage elements over the first dielectric layer, thermally oxidizing the plurality of discrete storage elements to form a second dielectrics over the plurality of discrete storage elements, and forming a gate electrode over the second dielectric layer, wherein a significant portion of the gate electrode is between pairs of the plurality of discrete storage elements. In one embodiment, portions of the gate electrode is in the spaces between the discrete storage elements and extends to more than half of the depth of the spaces.
摘要翻译： 一种形成半导体器件的方法包括在半导体衬底上形成第一电介质层，在第一介电层上形成多个离散存储元件，热氧化多个离散的存储元件，以在多个离散存储器上形成第二电介质 元件，并且在所述第二介电层上形成栅电极，其中所述栅电极的重要部分位于所述多个离散存储元件的对之间。 在一个实施例中，栅电极的部分位于离散存储元件之间的空间中并且延伸到空间深度的一半以上。
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公开(公告)号：US07456465B2
公开(公告)日：2008-11-25
申请号：US11240240
申请日：2005-09-30
IPC分类号： H01L29/788
CPC分类号： H01L21/28273 , B82Y10/00 , H01L29/42328 , H01L29/42332
摘要： A split gate memory cell has a select gate, a control gate, and a charge storage structure. The select gate includes a first portion located over the control gate and a second portion not located over the control gate. In one example, the first portion of the select gate has a sidewall aligned with a sidewall of the control gate and aligned with a sidewall of the charge storage structure. In one example, the control gate has a p-type conductivity. In one example, the gate can be programmed by a hot carrier injection operation and can be erased by a tunneling operation.
摘要翻译： 分离栅极存储单元具有选择栅极，控制栅极和电荷存储结构。 选择栅极包括位于控制栅极上方的第一部分和不位于控制栅极上方的第二部分。 在一个示例中，选择栅极的第一部分具有与控制栅极的侧壁对齐并与电荷存储结构的侧壁对准的侧壁。 在一个示例中，控制栅极具有p型导电性。 在一个示例中，门可以通过热载流子注入操作来编程，并且可以通过隧道操作来擦除。
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