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21.发明授权Method and built-in self-test apparatus for testing an integrated circuit which capture failure information for a selected failure 失效用于测试集成电路的方法和内置自检装置，其捕获所选故障的故障信息
公开(公告)号：US5912901A
公开(公告)日：1999-06-15
申请号：US823446
申请日：1997-03-24
IPC分类号： G01R31/28 , G01R31/3185 , G01R31/319 , G06F11/22 , G11C29/12
CPC分类号： G01R31/318555 , G01R31/2884 , G01R31/319
摘要： A built-in self-test (BIST) apparatus and method for testing an integrated circuit are disclosed which enable capture of failure data for a selected failure. The BIST apparatus comprises a clock generator, which generates at least a first clock signal, and a built-in self-tester, which applies predetermined input data patterns to the integrated circuit in response to the first clock signal. In addition, the BIST apparatus includes a data comparator for comparing output data received from the integrated circuit with expected output data. The data comparator detects a failure within the integrated circuit when the output data received from the integrated circuit differs from the expected output data. The BIST apparatus further includes a clock controller that disables the first clock signal in response to the detection of a selected occurrence of a failure. By enabling testing of the integrated circuit to be halted upon the occurrence of a selected failure, failure analysis of the integrated circuit is enhanced.
摘要翻译： 公开了一种用于测试集成电路的内置自检（BIST）装置和方法，其能够捕获所选故障的故障数据。 BIST装置包括产生至少第一时钟信号的时钟发生器和内置自测试器，其响应于第一时钟信号将预定的输入数据模式应用于集成电路。 此外，BIST装置包括用于将从集成电路接收的输出数据与预期输出数据进行比较的数据比较器。 当从集成电路接收的输出数据与预期输出数据不同时，数据比较器检测集成电路内的故障。 BIST装置还包括时钟控制器，其响应于所选择的故障发生的检测而禁用第一时钟信号。 通过在所选择的故障发生时能够对要停止的集成电路进行测试，增强了集成电路的故障分析。
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22.发明授权Bypass structure for a memory device and method to reduce unknown test values 有权用于存储器件的旁路结构和减少未知测试值的方法公开(公告)号：US08917566B2
公开(公告)日：2014-12-23
申请号：US13444229
申请日：2012-04-11
申请人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
发明人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
IPC分类号： G11C7/00
CPC分类号： G11C29/56004
摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.
摘要翻译： 本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。 在一个实施例中，公开了一种用于存储器件的旁路结构。 旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于 断言测试信号，使得来自存储器设备的输出的未知数据被旁路。
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23.发明授权Interleaving of memory repair data compression and fuse programming operations in single fusebay architecture 失效在单个保险丝架构中交织内存修复数据压缩和保险丝编程操作公开(公告)号：US08719648B2
公开(公告)日：2014-05-06
申请号：US13192051
申请日：2011-07-27
IPC分类号： G11C29/00
CPC分类号： G11C29/785 , G11C2029/0409 , H03M7/30
摘要： An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.
摘要翻译： 描述了在单个熔丝架结构中交织存储器修复数据压缩和熔丝编程操作的方法。 在一个实施例中，单个熔丝架结构包括与处理存储器修复数据压缩和熔丝编程操作的分割和交织方法一起使用的多页。 特别地，对于单个熔丝架结构中的每个页面，对存储器修复数据执行存储器修复数据压缩操作，随后对压缩存储器修复数据执行熔丝编程操作。
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公开(公告)号：US20130275821A1
公开(公告)日：2013-10-17
申请号：US13445187
申请日：2012-04-12
申请人： George M. BRACERAS , Albert M. CHU , Kevin W. Gorman , Michael R. OUELLETTE , Ronald A. PIRO , Daryl M. SEITZER , Rohit SHETTY , Thomas W. WYCKOFF
发明人： George M. BRACERAS , Albert M. CHU , Kevin W. Gorman , Michael R. OUELLETTE , Ronald A. PIRO , Daryl M. SEITZER , Rohit SHETTY , Thomas W. WYCKOFF
CPC分类号： G11C29/12 , G06F11/0793 , G11C17/00 , G11C29/4401 , G11C29/822
摘要： A read only memory (ROM) with redundancy and methods of use are provided. The ROM with redundancy includes a programmable array coupled to a repair circuit having one or more redundant repairs. The one or more redundant repairs include a word address match logic block, a data I/O address, and a tri-state buffer. The word address match logic block is provided to the tri-state buffer as a control input and the data I/O address is provided to the tri-state buffer as an input. An output of the tri-state buffer of each redundant repair is provided as a first input to one or more logic devices. One or more data outputs of a ROM bit cell array is provided as a second input to a respective one of the one or more logic devices.
摘要翻译： 提供了具有冗余性和使用方法的只读存储器（ROM）。 具有冗余的ROM包括耦合到具有一个或多个冗余修复的修复电路的可编程阵列。 一个或多个冗余修复包括字地址匹配逻辑块，数据I / O地址和三态缓冲器。 字地址匹配逻辑块作为控制输入提供给三态缓冲器，并且将数据I / O地址作为输入提供给三态缓冲器。 提供每个冗余修复的三态缓冲器的输出作为一个或多个逻辑器件的第一输入。 提供ROM位单元阵列的一个或多个数据输出作为一个或多个逻辑器件中的相应一个的第二输入。
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25.发明申请BYPASS STRUCTURE FOR A MEMORY DEVICE AND METHOD TO REDUCE UNKNOWN TEST VALUES 有权用于存储器件的旁路结构和减少未知测试值的方法公开(公告)号：US20130272072A1
公开(公告)日：2013-10-17
申请号：US13444229
申请日：2012-04-11
申请人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
发明人： Aaron J. Cummings , Michael T. Fragano , Kevin W. Gorman , Kelly A. Ockunzzi , Michael R. Ouellette
IPC分类号： G11C7/10
CPC分类号： G11C29/56004
摘要： Aspects of the invention provide a bypass structure for a memory device for reducing unknown test values, and a related method. In one embodiment, a bypass structure for a memory device is disclosed. The bypass structure includes: a logic gate configured to receive a test signal and a clock signal; and an output latch configured to receive an output of the logic gate, an output of the memory device, and a bypass data signal, wherein the output latch is configured to hold the bypass data signal and bypass the output of the memory device in response to asserting the test signal, such that unknown data from the output of the memory device is bypassed.
摘要翻译： 本发明的方面提供了一种用于减少未知测试值的存储器件的旁路结构以及相关方法。 在一个实施例中，公开了一种用于存储器件的旁路结构。 旁路结构包括：逻辑门，被配置为接收测试信号和时钟信号; 以及输出锁存器，被配置为接收逻辑门的输出，存储器件的输出和旁路数据信号，其中输出锁存器被配置为保持旁路数据信号并且绕过存储器件的输出以响应于 断言测试信号，使得来自存储器设备的输出的未知数据被旁路。
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公开(公告)号：US20130058176A1
公开(公告)日：2013-03-07
申请号：US13223949
申请日：2011-09-01
IPC分类号： G11C29/04
CPC分类号： G11C29/787 , G11C29/4401 , G11C2029/4402
摘要： Used fusebay storage elements are counted so that storage of data may begin at a first unused storage element. Repair register length and a number of previous passes are stored in a fuse header of a fusebay. When a bit of data is sent to the repair register, a repair register position tracker value is changed by one until it reaches a first value. When the first value is reached, a pass tracker value is changed by one. If the first value is not reached, the steps are repeated. A bit counter and/or a page counter may be included.
摘要翻译： 对所使用的熔断器存储元件进行计数，使得数据的存储可以在第一未使用的存储元件开始。 修理寄存器长度和许多以前的通行存储在保险丝盒的保险丝插头中。 当一些数据被发送到修复寄存器时，修复寄存器位置跟踪器值将被改变一到达到第一个值。 当达到第一个值时，通过跟踪器值改变一。 如果没有达到第一个值，则重复这些步骤。 可以包括位计数器和/或页计数器。
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27.发明申请INTERLEAVING OF MEMORY REPAIR DATA COMPRESSION AND FUSE PROGRAMMING OPERATIONS IN SINGLE FUSEBAY ARCHITECTURE 失效记忆体修复数据压缩和单个保险丝架构中的保险丝编程操作公开(公告)号：US20130031319A1
公开(公告)日：2013-01-31
申请号：US13192051
申请日：2011-07-27
IPC分类号： G06F12/06
CPC分类号： G11C29/785 , G11C2029/0409 , H03M7/30
摘要： An approach for interleaving memory repair data compression and fuse programming operations in a single fusebay architecture is described. In one embodiment, the single fusebay architecture includes a multiple of pages that are used with a partitioning and interleaving approach to handling memory repair data compression and fuse programming operations. In particular, for each page in the single fusebay architecture, a memory repair data compression operation is performed on memory repair data followed by a fuse programming operation performed on the compressed memory repair data.
摘要翻译： 描述了在单个熔丝架结构中交织存储器修复数据压缩和熔丝编程操作的方法。 在一个实施例中，单个熔丝架结构包括与处理存储器修复数据压缩和熔丝编程操作的分割和交织方法一起使用的多页。 特别地，对于单个熔丝架结构中的每个页面，对存储器修复数据执行存储器修复数据压缩操作，随后对压缩存储器修复数据执行熔丝编程操作。
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公开(公告)号：US07937632B2
公开(公告)日：2011-05-03
申请号：US12144703
申请日：2008-06-24
CPC分类号： G11C29/36 , G11C29/1201 , G11C29/48 , G11C2029/0401
摘要： A design structure is embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit. The design structure includes an input register coupled to a data processing unit input and a test operation mode and functional operation mode. In the test mode operation, the register operates in a clocked mode such that, during the test operation mode, the register propagates data to the data processing unit in response to a clock signal. In the functional operation mode, the register operates in a data flush mode such that the register propagates data to the data processing unit in response to the data. The functional mode is enabled by a flush enable signal and the test mode is enabled by an opposite state of the flush enable signal.
摘要翻译： 设计结构体现在用于设计，制造或测试集成电路的机器可读介质中。 该设计结构包括耦合到数据处理单元输入的输入寄存器和测试操作模式和功能操作模式。 在测试模式操作中，寄存器以时钟模式操作，使得在测试操作模式期间，寄存器响应于时钟信号将数据传播到数据处理单元。 在功能操作模式中，寄存器以数据刷新模式运行，使得寄存器响应于数据将数据传播到数据处理单元。 功能模式由刷新使能信号使能，测试模式通过刷新使能信号的相反状态使能。
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公开(公告)号：US20090319818A1
公开(公告)日：2009-12-24
申请号：US12144686
申请日：2008-06-24
IPC分类号： G06F1/06
CPC分类号： G01R31/318552 , G11C7/02 , G11C7/04 , G11C7/1072 , G11C29/023 , G11C29/028 , G11C29/1201 , G11C29/12015 , G11C29/48 , G11C2029/5602 , G11C2207/104
摘要： A method is provided for operating an interface between a first unit and a second unit supplying its data. The method includes switching control between LSSD_B and LSSD_C clocks and system clock (CLK) to provide a test mode of operation and a functional mode of operation to optimize setup and hold times depending on conditions under which the unit is operating. In the test mode, data is launched by the LSSD_C clock. In the functional mode, the data is launched by the system clock (CLK) to RAM. A method is also provided to determine which memory inputs should use a circuit that provides adequate setup and hold margins.
摘要翻译： 提供一种用于操作第一单元和提供其数据的第二单元之间的接口的方法。 该方法包括在LSSD_B和LSSD_C时钟之间的切换控制和系统时钟（CLK），以提供测试操作模式和功能操作模式，以根据单元运行的条件来优化建立和保持时间。 在测试模式下，数据由LSSD_C时钟启动。 在功能模式下，数据由系统时钟（CLK）发送到RAM。 还提供了一种方法来确定哪些存储器输入应该使用提供足够的建立和保持余量的电路。
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公开(公告)号：US20090251978A1
公开(公告)日：2009-10-08
申请号：US12101457
申请日：2008-04-11
IPC分类号： G11C29/44
CPC分类号： H03K19/018585 , H03K19/018557 , H03K19/018592
摘要： A method, an integrated circuit structure, and an associated design structure for the integrated circuit structure have a plurality of logic blocks, at least one of which is a redundant logic block. In addition, the structure includes a logic built-in self test device (LBIST) operatively connected to the logic blocks that determines the functionality of each of the logic blocks. An array of memory elements is included within the structure and is operatively connected to the logic blocks. At least one of the memory elements comprises a redundant memory element. The structure also includes an array built-in self test device (ABIST) operatively connected to the array of memory elements that determines the functionality of each of the memory elements. One feature is the use of a single controller operatively connected to the register, the logic blocks, and the memory elements. The single controller repairs both the logic blocks elements that have failing functionality and the memory elements that have failing functionality.
摘要翻译： 用于集成电路结构的方法，集成电路结构和相关联的设计结构具有多个逻辑块，其中至少一个是冗余逻辑块。 此外，该结构包括逻辑内置自检装置（LBIST），其可操作地连接到确定每个逻辑块的功能的逻辑块。 存储器元件阵列包括在结构内并且可操作地连接到逻辑块。 存储器元件中的至少一个包括冗余存储元件。 该结构还包括可操作地连接到确定每个存储器元件的功能的存储器元件阵列的阵列内置自检器件（ABIST）。 一个特征是使用可操作地连接到寄存器，逻辑块和存储器元件的单个控制器。 单个控制器修复具有故障功能的逻辑块元素和具有故障功能的存储器元件。
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