公开(公告)号：US5943507A

公开(公告)日：1999-08-24

申请号：US915154

申请日：1997-08-20

申请人： John H. Cornish ,  Shannon A. Wichman ,  Qadeer A. Qureshi

发明人： John H. Cornish ,  Shannon A. Wichman ,  Qadeer A. Qureshi

IPC分类号： G06F13/24 ,  G06F13/00

CPC分类号： G06F13/24

摘要： A computer system including an arrangement for programmably assigning interrupts to a larger set of interrupt channels. The computer system includes a microprocessing unit ("MPU" 102), a peripheral processing unit ("PPU" 110) that communicates with the MPU and a peripheral control unit ("PCU" 112) capable of communicating with the PPU and with at least one associated peripheral device. The PCU has associated therewith a first number, m, of interrupts for signalling to the MPU. The MPU has a second number, n, of interrupt channels over which interrupts are communicable to said MPU. A first register (IN1616) is provided in the PCU for storing a routing value representing the assignment of the m interrupts of the PCU to a selected subset of m channels of the n interrupt channels. A second register (IN1222) is provided in the PPU for storing the routing value. A number, m, connections are provided between the PCU and the PPU for transmitting the m interrupts from the PCU to the PPU. Finally, a logic unit (3820, 3830, 914) is provided that is responsive to the receipt of an interrupt on one of the m connections and to the stored routing value in the second register for communicating an interrupt to the MPU and for identifying to the MPU the m selected interrupt channels to which the communicated interrupt is assigned. Other devices, systems and methods are also disclosed.

摘要翻译： 一种计算机系统，包括用于可编程地将中断分配给更大的一组中断信道的装置。 计算机系统包括微处理单元（“MPU”102），与MPU通信的外围处理单元（“PPU”110）和能够与PPU进行通信的外围控制单元（“PCU”112） 一个相关的外围设备。 PCU与其相关联地具有用于向MPU发信号的中断的第一数量m。 MPU具有第二数量的n个中断通道，中断可以通过该中断通道传送到所述MPU。 在PCU中提供第一寄存器（IN1616），用于将表示PCU的m个中断的分配的路由值存储到n个中断信道的选定的m个信道的子集中。 PPU中提供了第二个寄存器（IN1222），用于存储路由值。 在PCU和PPU之间提供数字m连接，用于将m个中断从PCU发送到PPU。 最后，提供逻辑单元（3820,3830,914），其响应于在m个连接中的一个上接收到中断以及第二寄存器中存储的路由值，以将中断传送给MPU，并且用于识别 MPU分配了通信中断的m个选择的中断通道。 还公开了其他装置，系统和方法。

公开(公告)号：US5894578A

公开(公告)日：1999-04-13

申请号：US575685

申请日：1995-12-19

申请人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

发明人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

IPC分类号： G06F13/24 ,  G06F9/46

CPC分类号： G06F13/24

摘要： A programmable interrupt controller for use in computer systems including one or more CPUs is provided. The programmable interrupt controller includes an interrupt request interface, a central interrupt controller, random access memory, and at least one processor interface. The central interrupt controller systematically selects interrupt requests from the interrupt request interface. Information associated with each interrupt request is stored in the random access memory. The central interrupt controller access the information in the random access memory and uses the information and the state of the currently selected interrupt request to determine a next state for the currently selected interrupt request. The information is passed on to the processor interface to determine when and if the interrupt request should issue to one of the CPUs.

摘要翻译： 提供了一种用于包括一个或多个CPU的计算机系统的可编程中断控制器。 可编程中断控制器包括中断请求接口，中央中断控制器，随机存取存储器和至少一个处理器接口。 中央中断控制器系统地从中断请求接口中选择中断请求。 与每个中断请求相关联的信息存储在随机存取存储器中。 中央中断控制器访问随机存取存储器中的信息，并使用当前选择的中断请求的信息和状态来确定当前选择的中断请求的下一状态。 该信息被传递到处理器接口，以确定中断请求何时以及是否向其中一个CPU发布。

公开(公告)号：US5892956A

公开(公告)日：1999-04-06

申请号：US934261

申请日：1997-09-19

申请人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

发明人： Qadeer A. Qureshi ,  Joseph A. Bailey ,  Dan S. Mudgett

IPC分类号： G06F9/46 ,  G06F13/26

CPC分类号： G06F13/26

摘要： A programmable interrupt controller for use in a multiprocessing environment that can support a serial bus to send interrupt information to the processors. The interrupt serial bus has a data line to drive all the interrupt information to all the processors and a clock line to synchronize edges for the data stream. A third line, normally tri-stated, may be used to provide a parity error indication for the serial bus. The serial data includes a processor identification, a pin identification and state information. As the programmable interrupt controller sends the interrupt data on the serial bus, all the processors clock the data and check parity. If a processor finds a parity error, it drives the parity error indication low so that the information may be transmitted again. No processor will execute the command contained in the serial message before the time has elapsed for any of the processors to report a parity error. If there is no parity error, the processor accepts and decodes the message and asserts or deasserts the appropriate signal.

摘要翻译： 一种用于多处理环境的可编程中断控制器，可以支持串行总线向处理器发送中断信息。 中断串行总线具有数据线，用于将所有中断信息驱动到所有处理器和时钟线以同步数据流的边沿。 通常三通道的第三行可用于为串行总线提供奇偶校验错误指示。 串行数据包括处理器标识，引脚标识和状态信息。 由于可编程中断控制器在串行总线上发送中断数据，所有的处理器都会对数据进行计时并检查奇偶校验。 如果处理器发现奇偶校验错误，则将奇偶校验错误指示值驱动为低，以便再次发送信息。 没有处理器将在任何处理器报告奇偶校验错误的时间过去之前执行包含在串行消息中的命令。 如果没有奇偶校验错误，则处理器接受并解码消息，并声明或取消对相应信号的声明。

公开(公告)号：US07362645B2

公开(公告)日：2008-04-22

申请号：US10955356

申请日：2004-09-30

申请人： Qadeer A. Qureshi ,  John J. Vaglica ,  William C. Moyer ,  Ryan D. Bedwell

发明人： Qadeer A. Qureshi ,  John J. Vaglica ,  William C. Moyer ,  Ryan D. Bedwell

IPC分类号： G11C17/18 ,  G11C17/00 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C17/18

摘要： Storage circuitry (66) may be used to store the values of fuses (77) so that storage circuitry (66) can be read instead of fuses (77). By accessing the fuse values from storage circuitry (66) rather than from fuses (77), there will be no sense current to fuses (77) that may cause marginal fuse blowage for fuses that have not yet been blown. This helps to prevent the situation in which an unblown fuse is erroneously read as having been blown. The use of storage circuitry (66) thus significantly improves the reliability of fuse module (20). For some embodiments, selection storage circuitry (64) may be used to determine whether storage circuitry (66) may be read or whether one of fuses (77) must be read in order to retrieve the desired current fuse value. The fuse value stored in storage circuitry (66) can also be used as direct hardware signals (80).

摘要翻译： 存储电路（66）可以用于存储熔丝（77）的值，使得可以读取存储电路（66）而不是保险丝（77）。 通过从存储电路（66）而不是保险丝（77）访问熔丝值，对熔断器（77）将没有感应电流可能导致尚未熔断的熔断器的边缘熔断器。 这有助于防止未熔断的保险丝被错误地读取为已被吹灭的情况。 因此，存储电路（66）的使用显着地提高了熔丝模块（20）的可靠性。 对于一些实施例，可以使用选择存储电路（64）来确定是否可以读取存储电路（66），或者是否必须读取保险丝（77）之一以便检索所需的当前熔丝值。 存储在存储电路（66）中的熔丝值也可以用作直接硬件信号（80）。

公开(公告)号：US07295484B2

公开(公告)日：2007-11-13

申请号：US11685419

申请日：2007-03-13

申请人： Arnaldo R. Cruz ,  Qadeer A. Qureshi

发明人： Arnaldo R. Cruz ,  Qadeer A. Qureshi

IPC分类号： G11C7/00 ,  G11C7/04 ,  G11C5/06

CPC分类号： G11C11/406 ,  G11C11/40626

摘要： A system for controlling the refresh cycles of a DRAM cell array based upon a temperature measurement. During active mode, a refresh request indication based on a measured temperature is provided to a DRAM controller (e.g. of another integrated circuit die), wherein the DRAM controller initiates a refresh cycle of the DRAM cell array in response thereto. In a self refreshing mode, the DRAM controller does not initiate refresh cycles, but refresh cycles are performed by a controller on the integrated circuit die of the array based upon a temperature measurement.

公开(公告)号：US06510497B1

公开(公告)日：2003-01-21

申请号：US09207971

申请日：1998-12-09

申请人： Geoffrey S. Strongin ,  Qadeer A. Qureshi

发明人： Geoffrey S. Strongin ,  Qadeer A. Qureshi

IPC分类号： G06F1200

CPC分类号： G06F12/0215 ,  G06F13/1626

摘要： A method and system which will provide data processing systems having memory controllers with the ability to intelligently schedule accesses to system memory. The method and system provide a memory controller having a page-state sensitive memory arbiter. The method and system further include one or more memory state tracking units operably coupled to the page-state sensitive memory arbiter, and the one or more memory state tracking units operably coupled to a system memory. The one or more memory state tracking units operably coupled to a system memory further include the one or more memory state tracking units operably coupled to one or more system memory devices. The method and system track system memory status, monitor pending memory access requests, and schedule one or more pending memory access requests for execution dependent upon the system memory status and the pending memory access requests.

摘要翻译： 一种方法和系统，其将提供具有能够智能调度对系统存储器的访问的能力的具有存储器控制器的数据处理系统。 该方法和系统提供具有页状态敏感存储器仲裁器的存储器控​​制器。 该方法和系统还包括可操作地耦合到页状态敏感存储器仲裁器的一个或多个存储器状态跟踪单元，以及可操作地耦合到系统存储器的一个或多个存储器状态跟踪单元。 可操作地耦合到系统存储器的一个或多个存储器状态跟踪单元还包括可操作地耦合到一个或多个系统存储器件的一个或多个存储器状态跟踪单元。 所述方法和系统跟踪系统存储器状态，监视未决的存储器访问请求，并根据系统存储器状态和未决的存储器访问请求调度一个或多个待执行的待执行存储器访问请求以进行执行。

公开(公告)号：US06381683B1

公开(公告)日：2002-04-30

申请号：US09208522

申请日：1998-12-09

申请人： Geoffrey S. Strongin ,  Qadeer A. Qureshi

发明人： Geoffrey S. Strongin ,  Qadeer A. Qureshi

IPC分类号： G06F1200

CPC分类号： G06F12/0215

摘要： A method and system providing a memory controller having a destination-sensitive memory request reordering device. The destination-sensitive memory request reordering device includes a centralized state machine operably connected to one or more memory devices and one or more reorder and bank select engines. The centralized state machine is structured such that control information can be received from at least one of the one or more reorder and bank select engines over the one or more control lines. The centralized state machine is structured such that memory status information can be received from at least one of the one or more reorder and bank select engines over the one or more memory status lines, or such that memory status information can be determined by tracking past memory related activity. Additionally, the centralized state machine is structured to accept memory access requests having associated origin information. The centralized state machine executes the memory access requests based upon the associated origin information and the memory status information. Other embodiments function analogously, with the addition that the centralized state machine incorporates one or more device arbiter and state engines which function as autonomous units generally dedicated to one specific system memory device. The device arbiter and state engines receive identical inputs as discussed for the centralized state machine, except that typically each device arbiter and state engine is dedicated to one particular memory device, and thus generally receives memory status from the memory device with which it is associated via its dedicated memory status line.

摘要翻译： 一种提供具有目的地敏感存储器请求重新排序装置的存储器控​​制器的方法和系统。 目的地敏感存储器请求重排序设备包括可操作地连接到一个或多个存储器设备和一个或多个重新排序和存储体选择引擎的集中式状态机。 集中式状态机的结构使得可以通过一个或多个控制线路从一个或多个重新排序和分组选择引擎中的至少一个接收控制信息。 集中式状态机被构造成使得可以通过一个或多个存储器状态行从一个或多个重新排序和存储体选择引擎中的至少一个接收存储器状态信息，或者可以通过跟踪过去的存储器来确定存储器状态信息 相关活动。 此外，集中式状态机被构造为接受具有相关联的原始信息的存储器访问请求。 集中式状态机基于相关联的原始信息和存储器状态信息来执行存储器访问请求。 其他实施例类似地起作用，另外，集中式状态机包括一个或多个设备仲裁器和状态引擎，其作为一般专用于一个特定系统存储器设备的自主单元。 设备仲裁器和状态引擎接收与集中式状态机所讨论的相同的输入，除了通常每个设备仲裁器和状态引擎都专用于一个特定的存储设备，因此通常从与其相关联的存储器设备中接收存储器状态 其专用内存状态行。

公开(公告)号：US06226721B1

公开(公告)日：2001-05-01

申请号：US09208569

申请日：1998-12-09

申请人： Geoffrey S. Strongin ,  Qadeer A. Qureshi

发明人： Geoffrey S. Strongin ,  Qadeer A. Qureshi

IPC分类号： G06F1318

CPC分类号： G06F13/1626

摘要： A method and system for generating and utilizing speculative memory accesses in data processing systems. The method and system provide a memory controller having at least one origin-sensitive speculative memory access request generator. The origin-sensitive speculative memory access request generator is associated with one or more origins of memory access requests. In some embodiments, the origins are buses over which the one or more memory access request travel; in other embodiments the origins are sources of the one or more memory access requests. The origin-sensitive speculative memory access request generator monitors reorder buffers associated with the one or more origins, and in response to space in the reorder buffers generates speculative memory access requests of a type likely to be received by the reorder buffers in the future. The generated origin-related speculative memory access requests are received by a speculative memory access request response buffer checking-and-logic-control unit associated with system memory. The speculative memory access request response buffer checking-and-logic-control unit associated with system memory examines the state of system memory, and, if appropriate, executes some or all of the speculative memory access requests. Subsequent to execution, the responses to the speculative memory access requests are stored in a speculative memory access request response buffer, and thereafter such results are utilized to satisfy non-speculative requests subsequently received.

摘要翻译： 一种用于在数据处理系统中生成和利用推测存储器访问的方法和系统。 该方法和系统提供具有至少一个原点敏感推测存储器访问请求生成器的存储器控​​制器。 原点敏感的推测存储器访问请求生成器与存储器访问请求的一个或多个来源相关联。 在一些实施例中，起点是一个或多个存储器访问请求行进的总线; 在其他实施例中，起点是一个或多个存储器访问请求的源。 原点敏感推测存储器访问请求生成器监视与一个或多个源相关联的重新排序缓冲器，并且响应于重新排序缓冲器中的空间，将生成可能由重新排序缓冲器接收的类型的推测存储器访问请求。 生成的与源相关的推测存储器访问请求由与系统存储器相关联的推测存储器访问请求响应缓冲器检查和逻辑控制单元接收。 与系统存储器相关联的推测存储器访问请求响应缓冲器检查和逻辑控制单元检查系统存储器的状态，并且如果合适，执行部分或全部推测性存储器访问请求。 在执行之后，对推测存储器访问请求的响应被存储在推测存储器访问请求响应缓冲器中，此后，这些结果被用于满足随后接收的非推测性请求。

公开(公告)号：US20140129883A1

公开(公告)日：2014-05-08

申请号：US13668951

申请日：2012-11-05

申请人： Henning F. Spruth ,  Qadeer A. Qureshi ,  Reinaldo Silveira

发明人： Henning F. Spruth ,  Qadeer A. Qureshi ,  Reinaldo Silveira

IPC分类号： G11C29/12

CPC分类号： G11C29/12 ,  G01R31/3181 ,  G01R31/3187 ,  G11C7/20 ,  G11C7/24

摘要： Systems and methods for hardware-based initialization of memory circuitry. In some embodiments, a method may include, after completion and/or independently of an integrity test of a memory circuit, generating a sequence of random logic values using a Built-In-Self-Test (BIST) circuit. The method may further include initializing the memory circuit with the sequence of random logic values using the BIST circuit. In some implementations, the sequence of logic values may be generated using memory circuit identification, chip identification, and/or clock information as a seed state.

摘要翻译： 用于存储器电路的基于硬件的初始化的系统和方法。 在一些实施例中，方法可以在完成和/或独立于存储器电路的完整性测试之后包括使用内置自测试（BIST）电路生成随机逻辑值序列。 该方法还可以包括使用BIST电路以随机逻辑值的序列初始化存储器电路。 在一些实现中，可以使用存储器电路识别，芯片标识和/或时钟信息作为种子状态来生成逻辑值序列。

公开(公告)号：US20090016140A1

公开(公告)日：2009-01-15

申请号：US11777635

申请日：2007-07-13

申请人： Qadeer A. Qureshi ,  Sushama Davar ,  Thomas Jew

发明人： Qadeer A. Qureshi ,  Sushama Davar ,  Thomas Jew

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C11/41 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

摘要： A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.

摘要翻译： 在存储器的操作期间动态地调整集成电路上的存储器的电源电压。 存储器的操作包括以电源电压供电存储器。 在操作存储器的同时，集成电路的测试存储器同时供电。 测试存储器和存储器各自包括第一位单元配置类型的位单元。 基于测试存储器的测试，在操作存储器的同时调整电源电压的电压电平。 电压电平通过外部变化进行调整，以保证不会使存储器发生故障的值，同时也可以精确地最小化电源电压。 系统和方法可以用任何类型的存储器来实现。 存储器和测试存储器可以物理地实现为分离或散布在集成电路上。