公开(公告)号：US06337659B1

公开(公告)日：2002-01-08

申请号：US09426198

申请日：1999-10-25

Applicant: Sang-Gi Kim

Inventor： Sang-Gi Kim

IPC: H01Q326

CPC classification number: H04B7/0805 ,  H01Q1/246 ,  H01Q3/30 ,  H01Q25/008 ,  H04B7/10 ,  Y02D70/122 ,  Y02D70/442 ,  Y02D70/444

Abstract: A phased array antenna system having low power amplifiers reduces power loss through several tens meters high frequency cables. The antenna system for transmitting a signal in a base station, comprising: a phased array unit for selecting an input signal through one of a plurality of beam ports, for dividing the input signal into a plurality of signals and for outputting the plurality of signals through a plurality of array ports, each of the signal having a linear phase difference according to difference of propagation path; a switch for receiving the input signal from a base station, for selecting one of the plurality of beam ports of said phased array and for transmitting the input signal to the selected beam port, responsive to a control signal transmitted from the base station; a plurality of low power amplifiers for low power amplifying the plurality of signals inputted from the plurality of array ports of said phased array; and phased array antennas for radiating the plurality of signals from said plurality of low power amplifiers, thereby providing a spatial power summation into a direction of equiphase plane allowing effective radiated power sufficiently enough to cover a cell into a steered direction selected by said switch.

Abstract translation: 具有低功率放大器的相控阵天线系统通过数十米高频电缆降低功率损耗。 用于在基站中发送信号的天线系统，包括：相控阵单元，用于通过多个波束端口之一选择输入信号，用于将输入信号分成多个信号，并通过 多个阵列端口，每个信号根据传播路径的差异具有线性相位差; 用于从基站接收输入信号的开关，用于选择所述相控阵列的多个波束端口中的一个并响应于从基站发送的控制信号将输入信号发射到所选波束端口; 多个低功率放大器，用于低功率放大从所述相控阵列的多个阵列端口输入的多个信号; 以及用于从所述多个低功率放大器辐射多个信号的相控阵天线，由此向同相平面的方向提供空间功率求和，从而允许足够有效的辐射功率将小区覆盖成由所述开关选择的转向方向。

公开(公告)号：US08823299B2

公开(公告)日：2014-09-02

申请号：US13286455

申请日：2011-11-01

Applicant: Yil Suk Yang ,  Jongdae Kim ,  Sewan Heo ,  Sang Gi Kim ,  Jimin Oh ,  Minki Kim

Inventor： Yil Suk Yang ,  Jongdae Kim ,  Sewan Heo ,  Sang Gi Kim ,  Jimin Oh ,  Minki Kim

IPC: H02P6/00

CPC classification number: H02P6/182

Abstract: Disclosed is a power supply module for a hall sensorless BLDC motor, including: a high-voltage/large-current power device t applied with high voltage/large current and including a plurality of power devices driving the hall sensorless brushless direct current (BLDC) motor; a motor driving circuit sensing and controlling a positional signal or a velocity signal of the hall sensorless BLDC motor and generating a PWM control signal for controlling the hall sensorless BLDC motor; and a power device driving circuit driving the high-voltage/large-current power device according to the PWM control signal of the motor driving circuit, wherein the high-voltage/large-current power device, the power device driving circuit, and the motor driving circuit are CMOS-integrated on the same substrate.

Abstract translation: 本发明公开了一种霍尔无传感器BLDC电机的电源模块，包括：施加高电压/大电流的高压/大电流功率器件，并包括驱动霍尔无传感器无刷直流（BLDC）的多个功率器件， 发动机; 检测和控制霍尔无传感器BLDC电动机的位置信号或速度信号的电机驱动电路，并产生用于控制霍尔无传感器BLDC电动机的PWM控制信号; 以及根据所述电动机驱动电路的PWM控制信号驱动所述高电压/大电流功率器件的功率器件驱动电路，其中所述高压/大电流功率器件，所述功率器件驱动电路和所述电动机 CMOS驱动电路集成在同一基板上。

公开(公告)号：US08548281B2

公开(公告)日：2013-10-01

申请号：US12872881

申请日：2010-08-31

Applicant: Gyungock Kim ,  Jeong Woo Park ,  Jongbum You ,  Sang Gi Kim ,  Sanghoon Kim ,  In Gyoo Kim ,  Jiho Joo ,  Duk Jun Kim ,  Dongwoo Suh ,  Sahnggi Park ,  Ki Seok Jang ,  Junghyung Pyo ,  Kap-Joong Kim ,  Do Won Kim ,  Dae Seo Park

Inventor： Gyungock Kim ,  Jeong Woo Park ,  Jongbum You ,  Sang Gi Kim ,  Sanghoon Kim ,  In Gyoo Kim ,  Jiho Joo ,  Duk Jun Kim ,  Dongwoo Suh ,  Sahnggi Park ,  Ki Seok Jang ,  Junghyung Pyo ,  Kap-Joong Kim ,  Do Won Kim ,  Dae Seo Park

IPC: G02F1/025

CPC classification number: G02F1/025 ,  G02F2201/063

Abstract: Provided is an electro-optic modulating device. The electro-optic modulating device includes an optical waveguide with a vertical structure and sidewalls of the vertical structure are used to configure a junction.

Abstract translation: 提供了一种电光调制装置。 电光调制装置包括具有垂直结构的光波导，垂直结构的侧壁用于构造接合部。

公开(公告)号：US20120139463A1

公开(公告)日：2012-06-07

申请号：US13286455

申请日：2011-11-01

Applicant: Yil Suk Yang ,  Jongdae Kim ,  Sewan Heo ,  Sang Gi Kim ,  Jimin Oh ,  Minki Kim

Inventor： Yil Suk Yang ,  Jongdae Kim ,  Sewan Heo ,  Sang Gi Kim ,  Jimin Oh ,  Minki Kim

IPC: H02H7/122 ,  H02P27/00

CPC classification number: H02P6/182

Abstract: Disclosed is a power supply module for a hall sensorless BLDC motor, including: a high-voltage/large-current power device t applied with high voltage/large current and including a plurality of power devices driving the hall sensorless brushless direct current (BLDC) motor; a motor driving circuit sensing and controlling a positional signal or a velocity signal of the hall sensorless BLDC motor and generating a PWM control signal for controlling the hall sensorless BLDC motor; and a power device driving circuit driving the high-voltage/large-current power device according to the PWM control signal of the motor driving circuit, wherein the high-voltage/large-current power device, the power device driving circuit, and the motor driving circuit are CMOS-integrated on the same substrate.

Abstract translation: 本发明公开了一种霍尔无传感器BLDC电机的电源模块，包括：施加高电压/大电流的高压/大电流功率器件，并包括驱动霍尔无传感器无刷直流（BLDC）的多个功率器件， 发动机; 检测和控制霍尔无传感器BLDC电动机的位置信号或速度信号的电机驱动电路，并产生用于控制霍尔无传感器BLDC电动机的PWM控制信号; 以及根据所述电动机驱动电路的PWM控制信号驱动所述高电压/大电流功率器件的功率器件驱动电路，其中所述高压/大电流功率器件，所述功率器件驱动电路和所述电动机 CMOS驱动电路集成在同一基板上。

公开(公告)号：USD592163S1

公开(公告)日：2009-05-12

申请号：US29309402

申请日：2008-08-11

Applicant: Yong Ho Lee ,  A Reum Kwon ,  Jeong Rok Lee ,  Sang Gi Kim

Designer： Yong Ho Lee ,  A Reum Kwon ,  Jeong Rok Lee ,  Sang Gi Kim

公开(公告)号：US20090061378A1

公开(公告)日：2009-03-05

申请号：US12159522

申请日：2006-12-22

Applicant: In-Jae Kim ,  Sang-Gi Kim ,  Seung-Jae Park ,  Ji-Hun Jung ,  Chang-Seob Han ,  Seong-Chul Shin

Inventor： In-Jae Kim ,  Sang-Gi Kim ,  Seung-Jae Park ,  Ji-Hun Jung ,  Chang-Seob Han ,  Seong-Chul Shin

IPC: A61C7/20 ,  B21F43/00

CPC classification number: A61C7/20 ,  A61C2201/007 ,  B22F2999/00 ,  Y10T29/49568 ,  B22F5/12 ,  B22F7/04

Abstract: The present invention relates to an orthodontic wire and a manufacturing method thereof, and more particularly, to an orthodontic wire, which is not harmful to the human body and is capable of continuously holding the color of teeth, and a manufacturing method of the orthodontic wire. According to the present invention, there is provided an orthodontic wire, comprising a metal wire formed of a shape memory alloy material; a silver (Ag) film applied to a surface of the metal wire; and a polymer compound film applied to a surface of the silver (Ag) film to prevent the silver (Ag) film from being discolored.

Abstract translation: 本发明涉及一种正畸线及其制造方法，更具体地，涉及一种对人体无害并能够持续保持牙齿颜色的正畸线，以及正畸线的制造方法 。 根据本发明，提供了一种正畸线，其包括由形状记忆合金材料形成的金属线; 施加到金属线表面的银（Ag）膜; 以及施加到银（Ag）膜的表面上以防止银（Ag）膜变色的高分子化合物膜。

公开(公告)号：US07141464B2

公开(公告)日：2006-11-28

申请号：US11179983

申请日：2005-07-12

Applicant: Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

Inventor： Jong Moon Park ,  Kun Sik Park ,  Seong Wook Yoo ,  Yong Sun Yoon ,  Sang Gi Kim ,  Yoon Kyu Bae ,  Byung Won Lim ,  Jin Gun Koo ,  Bo Woo Kim

IPC: H01L21/338

CPC classification number: H01L21/28587

Abstract: Provided is a method of fabricating a T-type gate including the steps of: forming a first photoresist layer, a blocking layer and a second photoresist layer to a predetermined thickness on a substrate, respectively; forming a body pattern of a T-type gate on the second photoresist layer and the blocking layer; exposing a predetermined portion of the second photoresist layer to form a head pattern of the T-type gate, and performing a heat treatment process to generate cross linking at a predetermined region of the second photoresist layer except for the head pattern of the T-type gate; performing an exposure process on an entire surface of the resultant structure, and then removing the exposed portion; and forming a metal layer of a predetermined thickness on an entire surface of the resultant structure, and then removing the first photoresist layer, the blocking layer, the predetermined region of the second photoresist layer in which the cross linking are generated, and the metal layer, whereby it is possible to readily perform a compound semiconductor device manufacturing process, and to reduce manufacturing cost by means of the increase of manufacturing yield and the simplification of manufacturing processes.

Abstract translation: 提供一种制造T型栅极的方法，包括以下步骤：分别在衬底上形成预定厚度的第一光致抗蚀剂层，阻挡层和第二光致抗蚀剂层; 在所述第二光致抗蚀剂层和所述阻挡层上形成T型栅极的主体图案; 暴露第二光致抗蚀剂层的预定部分以形成T型栅极的头部图案，并且进行热处理工艺以在除了T型的头部图案之外的第二光致抗蚀剂层的预定区域处产生交联 门; 在所得结构的整个表面上进行曝光处理，然后去除所述暴露部分; 在所得结构的整个表面上形成预定厚度的金属层，然后去除第一光致抗蚀剂层，阻挡层，产生交联的第二光致抗蚀剂层的预定区域和金属层 ，由此可以容易地进行化合物半导体器件制造工艺，并且通过增加制造成品率和简化制造工艺来降低制造成本。

公开(公告)号：US06852597B2

公开(公告)日：2005-02-08

申请号：US10071127

申请日：2002-02-08

Applicant: Il-Yong Park ,  Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Dae Woo Lee ,  Roh Tae Moon ,  Yang Yil Suk

Inventor： Il-Yong Park ,  Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Dae Woo Lee ,  Roh Tae Moon ,  Yang Yil Suk

IPC: H01L21/336 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/7813 ,  H01L29/41766 ,  H01L29/41775 ,  H01L29/7802

Abstract: A method for fabricating a power semiconductor device having a trench gate structure is provided. An epitaxial layer of a first conductivity type having a low concentration and a body region of a second conductivity type are sequentially formed on a semiconductor substrate of the first conductivity type having a high concentration. An oxide layer pattern is formed on the body region. A first trench is formed using the oxide layer pattern as an etching mask to perforate a predetermined portion of the body region having a first thickness. A body contact region of the second conductivity type having a high concentration is formed to surround the first trench by impurity ion implantation using the oxide layer pattern as an ion implantation mask. First spacer layers are formed to cover the sidewalls of the first trench and the sidewalls of the oxide layer pattern. A second trench is formed using the oxide layer pattern and the first spacer layers as etching masks to perforate a predetermined portion of the body region having a second thickness greater than the first thickness. A source region of the first conductivity type having a high concentration is formed to surround the second trench by impurity ion implantation using the oxide layer pattern and the first spacer layers as ion implantation masks. Second spacer layers are formed to cover the sidewalls of the second trench and the sidewalls of the first spacer layers. A third trench is formed to a predetermined depth of the epitaxial layer using the oxide layer pattern, the first spacer layers, and the second spacer layers as etching masks. A gate insulating layer is formed in the third trench. A gate conductive pattern is formed in the gate insulating layer. An oxide layer is formed on the gate conductive layer pattern. The first and second spacer layers are removed. A first metal electrode layer is formed to be electrically connected to the source region and the body contact region. A second metal electrode layer is formed to be electrically connected to the gate conductive layer pattern. A third metal electrode layer is formed to be electrically connected to the semiconductor substrate.

公开(公告)号：US06534365B2

公开(公告)日：2003-03-18

申请号：US09726910

申请日：2000-11-29

Applicant: Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

Inventor： Jong Dae Kim ,  Sang Gi Kim ,  Jin Gun Koo ,  Kee Soo Nam ,  Dae Woo Lee ,  Tae Moon Roh

IPC: H01L21336

CPC classification number: H01L29/7813 ,  H01L29/0847 ,  H01L29/42368

Abstract: A method of fabricating a vertical TDMOS power device using sidewall spacers and a self-align technique and a TDMOS power device of the same. The TDMOS is fabricated using only 3 masks and a source is formed using the self-align technique to embody a highly integrated trench formation. During the process, ion implantation of high concentration into the bottom of the trench makes a thick oxide film grow on the bottom and the corner of the gate, so that electrical characteristic, specifically leakage current and breakdown voltage of the device can be improved. Also, process steps can be much decreased to lower process cost, high integration is possible, and reliability of the device can be improved.

Abstract translation: 使用侧壁间隔物和自对准技术制造垂直TDMOS功率器件的方法以及使用其的TDMOS功率器件。 TDMOS仅使用3个掩模制造，并且使用自对准技术形成源以体现高度集成的沟槽形成。 在此过程中，高浓度离子注入沟槽的底部使得厚的氧化膜在栅极的底部和拐角处生长，从而可以提高器件的电气特性，特别是漏电流和击穿电压。 此外，可以大大降低工艺步骤以降低工艺成本，可以实现高集成度，并且可以提高器件的可靠性。

公开(公告)号：US20120098057A1

公开(公告)日：2012-04-26

申请号：US13228479

申请日：2011-09-09

Applicant: Sang Gi KIM ,  Jin-Gun Koo ,  Seong Wook Yoo ,  Jong-Moon Park ,  Jin Ho Lee ,  Kyoung Il Na ,  Yil Suk Yang ,  Jongdae Kim

Inventor： Sang Gi KIM ,  Jin-Gun Koo ,  Seong Wook Yoo ,  Jong-Moon Park ,  Jin Ho Lee ,  Kyoung Il Na ,  Yil Suk Yang ,  Jongdae Kim

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7813 ,  H01L21/2255 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/1095 ,  H01L29/66727 ,  H01L29/66734 ,  H01L29/7811

Abstract: Provided are a semiconductor device and a method of fabricating the same. The method includes: forming a trench in a semiconductor substrate of a first conductive type; forming a trench dopant containing layer including a dopant of a second conductive type on a sidewall and a bottom surface of the trench; forming a doping region by diffusing the dopant in the trench dopant containing layer into the semiconductor substrate; and removing the trench dopant containing layer.

Abstract translation: 提供半导体器件及其制造方法。 该方法包括：在第一导电类型的半导体衬底中形成沟槽; 在所述沟槽的侧壁和底表面上形成包含第二导电类型的掺杂剂的沟槽掺杂剂层; 通过将所述沟槽掺杂剂含量层中的掺杂剂扩散到所述半导体衬底中来形成掺杂区域; 并去除含沟槽掺杂剂层。