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    Apparatus and method for directing micro architectural memory region accesses
    23.
    发明授权
    Apparatus and method for directing micro architectural memory region accesses 有权
    用于指导微架构存储器区域访问的装置和方法

    公开(公告)号：US08521969B2

    公开(公告)日：2013-08-27

    申请号：US11546710

    申请日：2006-10-11

    Applicant: Martin G. Dixon ,  Scott D. Rodgers ,  James P. Held ,  Bill Alexander ,  Larry O. Smith ,  Scott H. Robinson ,  Sham M. Datta

    Inventor： Martin G. Dixon ,  Scott D. Rodgers ,  James P. Held ,  Bill Alexander ,  Larry O. Smith ,  Scott H. Robinson ,  Sham M. Datta

    IPC: G06F12/00

    CPC classification number: G06F21/79 ,  G06F12/1441 ,  G06F2221/2141

    Abstract: In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

    Abstract translation: 在一个实施例中，存储在系统存储器内的信息的存储器访问请求通过集成电路。 系统存储器可以包括用于存储指令和/或数据的微架构存储器区域，其中微架构存储器区域将被微架构代理程序唯一地访问。集成电路可以包括存储器访问控制器以引导存储器访问请求 如果存储器访问指导者确定存储器访问请求包括至少一个微架构存储器区域内的位置，并且微架构代理程序在微架构存储器区域访问模式下操作，则向微架构存储器区域发送。

    Address generation unit with segmented addresses in a mircroprocessor
    25.
    发明授权
    Address generation unit with segmented addresses in a mircroprocessor 失效
    在微处理器中具有分段地址的地址生成单元

    公开(公告)号：US5590297A

    公开(公告)日：1996-12-31

    申请号：US176066

    申请日：1994-01-04

    Applicant: Kamla P. Huck ,  Scott D. Rodgers ,  Andrew F. Glew

    Inventor： Kamla P. Huck ,  Scott D. Rodgers ,  Andrew F. Glew

    IPC: G06F9/34 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F12/00

    CPC classification number: G06F12/1036 ,  G06F12/0292

    Abstract: A microprocessor comprising an execution unit for performing arithmetic functions, a fetch unit for determining which entry is to be accessed, an issue unit for accessing the entry from storage in a memory, and an address generation unit for generating an address for that entry. Portions of the base and limit values used for generating the address are stored in separate segments. These separate portions are rearranged so as to form a segment having contiguous base and limit bits. The contiguous base and limit values are then stored in a register file. Copies of the base and limit are stored in control registers and broadcast to other units. Furthermore, a resettable null bit is stored in another register. In addition, the AGU includes a means for selecting a particular field of the register file and performing read/write operations on the selected file.

    Abstract translation: 一种微处理器，包括用于执行算术功能的执行单元，用于确定要访问的条目的提取单元，用于从存储器中的存储访问该条目的发布单元，以及用于生成该条目的地址的地址生成单元。 用于生成地址的基本部分和限制值存储在单独的段中。 这些分离的部分被重新排列，以形成具有连续的基极和极限位的段。 然后将连续的基数和极限值存储在寄存器文件中。 基数和限制副本存储在控制寄存器中并广播到其他单元。 此外，可复位的无效位存储在另一个寄存器中。 此外，AGU包括用于选择寄存器文件的特定字段并对所选择的文件执行读/写操作的装置。

    System, method, and apparatus for a cache flush of a range of pages and TLB invalidation of a range of entries
    27.
    发明授权
    System, method, and apparatus for a cache flush of a range of pages and TLB invalidation of a range of entries 有权
    用于一系列页面的缓存刷新和一系列条目的TLB无效的系统，方法和装置

    公开(公告)号：US08214598B2

    公开(公告)日：2012-07-03

    申请号：US12644547

    申请日：2009-12-22

    Applicant: Martin G. Dixon ,  Scott D. Rodgers

    Inventor： Martin G. Dixon ,  Scott D. Rodgers

    IPC: G06F13/00

    CPC classification number: G06F12/1009 ,  G06F12/0891 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/683

    Abstract: Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.

    Abstract translation: 描述了用于执行多个高速缓存行的刷新和/或多个翻译后备缓冲器（TLB）条目的无效的系统，方法和装置。 在一种这样的方法中，为了冲洗处理器的多个高速缓存行，包括指示处理器的多个高速缓存行将被刷新的第一字段的单个指令并且响应于单个指令，刷新多个高速缓存 处理器的行。

    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE
    28.
    发明申请
    INSTRUCTION SET EXTENSION USING 3-BYTE ESCAPE OPCODE 有权
    使用3字节ESCAPE操作码的指令集扩展

    公开(公告)号：US20110173418A1

    公开(公告)日：2011-07-14

    申请号：US13070908

    申请日：2011-03-24

    Applicant: James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

    Inventor： James S. Coke ,  Peter J. Ruscito ,  Masood Tahir ,  David B. Jackson ,  Ves A. Naydenov ,  Scott D. Rodgers ,  Bret L. Toll ,  Frank Binns

    IPC: G06F9/30

    CPC classification number: G06F9/30149 ,  G06F9/30025 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30185

    Abstract: A method, apparatus and system are disclosed for decoding an instruction in a variable-length instruction set. The instruction is one of a set of new types of instructions that uses a new escape code value, which is two bytes in length, to indicate that a third opcode byte includes the instruction-specific opcode for a new instruction. The new instructions are defined such the length of each instruction in the opcode map for one of the new escape opcode values may be determined using the same set of inputs, where each of the inputs is relevant to determining the length of each instruction in the new opcode map. For at least one embodiment, the length of one of the new instructions is determined without evaluating the instruction-specific opcode.

    Abstract translation: 公开了用于对可变长度指令集中的指令进行解码的方法，装置和系统。 该指令是一组新的指令之一，它使用长度为两个字节的新的转义码值来指示第三个操作码字节包含新指令的指令特定操作码。 定义新指令，可以使用相同的一组输入来确定新的转义操作码值之一的操作码映射中每个指令的长度，其中每个输入与确定新指令中的每个指令的长度相关 操作码地图。 对于至少一个实施例，在不评估指令特定操作码的情况下确定新指令之一的长度。

    SYSTEM, METHOD, AND APPARATUS FOR A CACHE FLUSH OF A RANGE OF PAGES AND TLB INVALIDATION OF A RANGE OF ENTRIES
    29.
    发明申请
    SYSTEM, METHOD, AND APPARATUS FOR A CACHE FLUSH OF A RANGE OF PAGES AND TLB INVALIDATION OF A RANGE OF ENTRIES 有权
    系统，方法和装置，用于高速缓存页面和TLB无效的入口范围

    公开(公告)号：US20110153952A1

    公开(公告)日：2011-06-23

    申请号：US12644547

    申请日：2009-12-22

    Applicant: Martin G. Dixon ,  Scott D. Rodgers

    Inventor： Martin G. Dixon ,  Scott D. Rodgers

    IPC: G06F12/08 ,  G06F12/00 ,  G06F12/10

    CPC classification number: G06F12/1009 ,  G06F12/0891 ,  G06F12/1027 ,  G06F2212/1016 ,  G06F2212/683

    Abstract: Systems, methods, and apparatus for performing the flushing of a plurality of cache lines and/or the invalidation of a plurality of translation look-aside buffer (TLB) entries is described. In one such method, for flushing a plurality of cache lines of a processor a single instruction including a first field that indicates that the plurality of cache lines of the processor are to be flushed and in response to the single instruction, flushing the plurality of cache lines of the processor.

    Abstract translation: 描述了用于执行多个高速缓存行的刷新和/或多个翻译后备缓冲器（TLB）条目的无效的系统，方法和装置。 在一种这样的方法中，为了冲洗处理器的多个高速缓存行，包括指示处理器的多个高速缓存行将被刷新的第一字段的单个指令并且响应于单个指令，刷新多个高速缓存 处理器的行。

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