公开(公告)号：US20080091917A1

公开(公告)日：2008-04-17

申请号：US11546710

申请日：2006-10-11

申请人： Martin G. Dixon ,  Scott D. Rodgers ,  James P. Held ,  Bill Alexander ,  Larry O. Smith ,  Scott H. Robinson ,  Sham M. Datta

发明人： Martin G. Dixon ,  Scott D. Rodgers ,  James P. Held ,  Bill Alexander ,  Larry O. Smith ,  Scott H. Robinson ,  Sham M. Datta

IPC分类号： G06F15/76

CPC分类号： G06F21/79 ,  G06F12/1441 ,  G06F2221/2141

摘要： In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

摘要翻译： 在一个实施例中，存储在系统存储器内的信息的存储器访问请求通过集成电路。 系统存储器可以包括用于存储指令和/或数据的微架构存储器区域，其中微架构存储器区域将被微架构代理程序唯一地访问。集成电路可以包括存储器访问控制器以引导存储器访问请求 如果存储器访问指导者确定存储器访问请求包括至少一个微架构存储器区域内的位置，并且微架构代理程序在微架构存储器区域访问模式下操作，则向微架构存储器区域发送。

公开(公告)号：US08521969B2

公开(公告)日：2013-08-27

申请号：US11546710

申请日：2006-10-11

申请人： Martin G. Dixon ,  Scott D. Rodgers ,  James P. Held ,  Bill Alexander ,  Larry O. Smith ,  Scott H. Robinson ,  Sham M. Datta

发明人： Martin G. Dixon ,  Scott D. Rodgers ,  James P. Held ,  Bill Alexander ,  Larry O. Smith ,  Scott H. Robinson ,  Sham M. Datta

IPC分类号： G06F12/00

CPC分类号： G06F21/79 ,  G06F12/1441 ,  G06F2221/2141

摘要： In an embodiment, memory access requests for information stored within a system memory pass through an integrated circuit. The system memory may include a micro-architectural memory region to store instructions and/or data, where the micro-architectural memory region is to be exclusively accessible by a micro-architectural agent The integrated circuit may include memory access director to direct memory access requests to the micro-architectural memory region if the memory access director determines that the memory access request includes a location within the at least one micro-architectural memory region and the micro-architectural agent is operating in a micro-architectural memory region access mode.

摘要翻译： 在一个实施例中，存储在系统存储器内的信息的存储器访问请求通过集成电路。 系统存储器可以包括用于存储指令和/或数据的微架构存储器区域，其中微架构存储器区域将被微架构代理程序唯一地访问。集成电路可以包括存储器访问控制器以引导存储器访问请求 如果存储器访问指导者确定存储器访问请求包括至少一个微架构存储器区域内的位置，并且微架构代理程序在微架构存储器区域访问模式下操作，则向微架构存储器区域发送。

公开(公告)号：US08838935B2

公开(公告)日：2014-09-16

申请号：US12890585

申请日：2010-09-24

申请人： Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

发明人： Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

IPC分类号： G06F12/00 ,  G06F12/10 ,  G06F12/02

CPC分类号： G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

摘要： In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries.

摘要翻译： 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。 此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。 该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。

公开(公告)号：US07370160B2

公开(公告)日：2008-05-06

申请号：US11171993

申请日：2005-06-29

申请人： Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson ,  Dion Rodgers ,  David Koufaty ,  Richard A. Uhlig ,  Camron B. Rust ,  Larry O. Smith ,  Rupin H. Vakharwala

发明人： Gilbert Neiger ,  Steven M. Bennett ,  Andrew V. Anderson ,  Dion Rodgers ,  David Koufaty ,  Richard A. Uhlig ,  Camron B. Rust ,  Larry O. Smith ,  Rupin H. Vakharwala

IPC分类号： G06F12/00

CPC分类号： G06F12/1009 ,  G06F9/45537

摘要： A processor, capable of operation in a host machine, including memory management logic to support a plurality of memory types for a physical memory access by the processor, and virtualization support logic to determine a host memory type for a reference to a memory location by a guest in a virtual machine executable on the processor based at least in part on a memory type field stored in an entry of an extended paging table of a virtualization support system of the host machine (extended memory type field), to determine a guest memory type for the reference to the memory location, and to determine an effective memory type based on at least one of the host memory type and the guest memory type.

摘要翻译： 能够在主机中操作的处理器，包括用于支持由处理器进行物理存储器访问的多种存储器类型的存储器管理逻辑，以及虚拟化支持逻辑，以通过以下方式来确定用于引用存储器位置的主机存储器类型 至少部分地基于存储在主机的虚拟化支持系统（扩展存储器类型字段）的扩展寻呼表的条目中的存储器类型字段来在处理器上执行的虚拟机中的客户端，以确定客户机存储器类型 用于引用存储器位置，并且基于主机存储器类型和来宾存储器类型中的至少一个来确定有效的存储器类型。

公开(公告)号：US20120079232A1

公开(公告)日：2012-03-29

申请号：US12890585

申请日：2010-09-24

申请人： Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

发明人： Glenn Hinton ,  Madhavan Parthasarathy ,  Rajesh Parthasarathy ,  Muthukumar Swaminathan ,  Raj Ramanujan ,  David Zimmerman ,  Larry O. Smith ,  Adrian C. Moga ,  Scott J. Cape ,  Wayne A. Downer ,  Robert S. Chappell

IPC分类号： G06F12/10

CPC分类号： G06F12/1027 ,  G06F12/023 ,  G06F12/0292 ,  G06F12/06 ,  G06F12/1009 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/151 ,  G06F2212/205 ,  G06F2212/651 ,  Y02D10/13

摘要： An apparatus, method, machine-readable medium, and system are disclosed. In one embodiment the apparatus is a micro-page table engine that includes logic that is capable of receiving a memory page request for a page in global memory address space. The apparatus also includes a translation lookaside buffer (TLB) that is capable of storing one or more memory page address translations. Additionally, the apparatus also has a page miss handler capable of performing a micro physical address lookup in a page miss handler tag table in response to the TLB not storing the memory page address translation for the page of memory referenced by the memory page request. The apparatus also includes memory management logic that is capable of managing the page miss handler tag table entries. The micro-page table engine allows the TLB to be an agent that determines whether data in a two-level memory hierarchy is in a hot region of memory or in a cold region of memory. When data is in the cold region of memory, the micro-page table engine fetches the data to the hot memory and a hot memory block is then pushed out to the cold memory area.

摘要翻译： 公开了一种装置，方法，机器可读介质和系统。 在一个实施例中，该装置是微页表引擎，其包括能够接收全局存储器地址空间中的页面的存储器页面请求的逻辑。 该装置还包括能够存储一个或多个存储器页面地址转换的翻译后备缓冲器（TLB）。 此外，该设备还具有能够响应于TLB不存储由存储器寻呼请求引用的存储器页面的存储器页面地址转换而在页面未命中处理器标签表中执行微物理地址查找的页面未命中处理程序。 该装置还包括能够管理页面未命中处理程序标签表条目的存储器管理逻辑。 微页表引擎允许TLB作为一个代理，确定二级存储器层次结构中的数据是在存储器的热区域还是在存储器的冷区域。 当数据处于存储器的冷区域时，微页表引擎将数据读取到热存储器，然后将热存储器块推出到冷存储器区域。

公开(公告)号：US07849465B2

公开(公告)日：2010-12-07

申请号：US11134687

申请日：2005-05-19

申请人： Xiang Zou ,  Hong Wang ,  Scott Dion Rodgers ,  Darrell D. Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry O. Smith ,  James B. Crossland ,  Chris J. Newburn

发明人： Xiang Zou ,  Hong Wang ,  Scott Dion Rodgers ,  Darrell D. Boggs ,  Bryant Bigbee ,  Shivanandan Kaushik ,  Anil Aggarwal ,  Ittai Anati ,  Doron Orenstein ,  Per Hammarlund ,  John Shen ,  Larry O. Smith ,  James B. Crossland ,  Chris J. Newburn

IPC分类号： G06F9/46 ,  G06F13/24 ,  G06F7/38

CPC分类号： G06F9/3851 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/4843 ,  G06F11/3409 ,  G06F11/348 ,  G06F2201/86 ,  G06F2201/88 ,  G06F2201/885

摘要： Method, apparatus, and system for a programmable event driven yield mechanism that may activate other threads. The yield mechanism may allow triggering of a service thread that may execute currently with a main thread upon occurrence of an architecturally-defined condition. The service thread may be activated, in response to the condition, with limited intervention of an operating system. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and a monitor to detect an architecturally-defined condition. The apparatus may include an event handler to handle a yield event generated when the architecturally-defined condition has been detected. An architectural mechanism, including processor instructions and channel registers, may be utilized to allow user-level code to enable the yield event mechanism. Other embodiments are also described and claimed.

摘要翻译： 用于可激活其他线程的可编程事件驱动产量机制的方法，装置和系统。 收益机制可以允许在出现体系结构定义的条件时触发可以执行当前与主线程的服务线程。 响应于条件，可以在操作系统的有限干预下激活服务线程。 在一个实施例中，装置包括执行多个指令的执行资源和监视器以检测体系结构定义的条件。 该装置可以包括事件处理程序，用于处理当检测到体系结构定义的条件时产生的产出事件。 可以使用包括处理器指令和通道寄存器在内的架构机制来允许用户级代码来实现产出事件机制。 还描述和要求保护其他实施例。

公开(公告)号：US5493667A

公开(公告)日：1996-02-20

申请号：US15541

申请日：1993-02-09

申请人： Scott B. Huck ,  Konrad K. Lai ,  Sunil R. Shenoy ,  Larry O. Smith

发明人： Scott B. Huck ,  Konrad K. Lai ,  Sunil R. Shenoy ,  Larry O. Smith

IPC分类号： G06F12/08 ,  G06F12/12

CPC分类号： G06F12/126 ,  G06F12/0864

摘要： An instruction locking apparatus and method for a cache memory allowing execution time predictability and high speed performance. The present invention implements a cache locking scheme in a two set associative instruction cache that utilizes a specially designed Least Recently Used (LRU) unit to effectively lock a first portion of the instruction cache to allow high speed and predictable execution time for time critical program code sections residing in the first portion while leaving another portion of the instruction cache free to operate as an instruction cache for other, non-critical, code sections. The present invention provides the above features in a system that is virtually transparent to the program code and does not require a variety of complex or specialized instructions or address coding methods. The present invention is flexible in that the two set associative instruction cache is transformed into what may be thought of as a static RAM in cache, and in addition, a direct map cache unit. Several different time critical code sections may be loaded and locked into the cache at different times.

摘要翻译： 一种用于缓存的指令锁定装置和方法，其允许执行时间可预测性和高速性能。 本发明在两组关联指令高速缓冲存储器中实现高速缓存锁定方案，其利用专门设计的最近使用（LRU）单元来有效地锁定指令高速缓存的第一部分，以允许用于时间关键程序代码的高速度和可预测的执行时间 驻留在第一部分中的部分，同时使指令高速缓存的另一部分可自由地作为用于其他非关键代码段的指令高速缓存。 本发明在系统中提供对程序代码实际上是透明的并且不需要各种复杂或专门的指令或地址编码方法的上述特征。 本发明的灵活性在于，将两组关联指令高速缓存转换成可以被认为是高速缓存中的静态RAM的内容，另外还有直接映射缓存单元。 可以在不同的时间将几个不同的时间关键代码段加载并锁定到高速缓存中。