公开(公告)号：US20070184649A1

公开(公告)日：2007-08-09

申请号：US11348428

申请日：2006-02-06

申请人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

发明人： Kyoung-Woo Lee ,  Seung-Man Choi ,  Ja-Hum Ku ,  Ki-Chul Park ,  Sun Kim

IPC分类号： H01L21/4763

CPC分类号： H01L21/76808 ,  H01L21/31144

摘要： Methods of forming integrated circuit devices include patterning an electrically insulating layer to support dual-damascene interconnect structures therein. The steps of patterning the electrically insulating layer include using multiple planarization layers having different porosity characteristics. Forming an interconnect structure within an integrated circuit device may include forming an electrically insulating layer on a substrate and forming at least one via hole extending at least partially through the electrically insulating layer. The at least one via hole is filled with a first electrically insulating material having a first porosity. The filled at least one via hole is then covered with a second electrically insulating material layer having a second porosity lower than the first porosity. The second electrically insulating material layer is selectively etched back to expose a first portion of the first electrically insulating material in the at least one via hole. The electrically insulating layer is selectively etched to define a trench therein that exposes a second portion of the first electrically insulating material in the at least one via hole. The first electrically insulating material, which has a relatively high degree of porosity, is then removed from the at least one via hole. This removal step may be performed using a relatively mild ashing process because of the high porosity of the first electrically insulating material.

摘要翻译： 形成集成电路器件的方法包括图案化电绝缘层以支持其中的双镶嵌互连结构。 图案化电绝缘层的步骤包括使用具有不同孔隙特性的多个平坦化层。 在集成电路器件内形成互连结构可以包括在衬底上形成电绝缘层，并形成至少部分穿过电绝缘层延伸的至少一个通孔。 至少一个通孔填充有具有第一孔隙率的第一电绝缘材料。 填充的至少一个通孔然后被具有低于第一孔隙率的第二孔隙率的第二电绝缘材料层覆盖。 选择性地回蚀第二电绝缘材料层以暴露至少一个通孔中的第一电绝缘材料的第一部分。 电绝缘层被选择性蚀刻以在其中限定其中的沟槽，其暴露出至少一个通孔中的第一电绝缘材料的第二部分。 然后从该至少一个通孔去除具有较高孔隙率的第一电绝缘材料。 由于第一电绝缘材料的高孔隙率，该去除步骤可以使用相对温和的灰化过程进行。

公开(公告)号：US20060177630A1

公开(公告)日：2006-08-10

申请号：US11336905

申请日：2006-01-23

申请人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

发明人： Sun-jung Lee ,  Soo-geun Lee ,  Hong-jae Shin ,  Andrew-tae Kim ,  Seung-man Choi ,  Bong-seok Suh

IPC分类号： B32B3/04

CPC分类号： H01L21/76877 ,  H01L21/7684 ,  H01L21/76883 ,  Y10T428/24207

摘要： A metal interconnection of a semiconductor device, formed using a damascene process, has large grains and yet a smooth surface. First, a barrier layer and a metal layer are sequentially formed in an opening in an interlayer dielectric layer. A CMP process is carried out on the metal layer to form a metal interconnection remaining within the opening. Then, the metal interconnection is treated with plasma. The plasma treatment creates compressive stress in the metal interconnection, which stress produces hillocks at the surface of the metal interconnection. In addition, the plasma treatment process causes grains of the metal to grow, especially when the design rule is small, to thereby decrease the resistivity of the metal interconnection. The hillocks are then removed by a CMP process aimed at polishing the portion of the barrier layer that extends over the upper surface of the interlayer dielectric layer. Finally, a capping insulating layer is formed. The intentional forming of hillocks by the plasma treatment process at weak portions of the metal interconnection and the subsequent removal of the hillocks greatly reduces the possibility of any additional hillocks being produced at the surface of the metal interconnection, especially when the capping layer is formed.

摘要翻译： 使用镶嵌工艺形成的半导体器件的金属互连具有大的晶粒并且具有光滑的表面。 首先，在层间电介质层的开口中依次形成阻挡层和金属层。 在金属层上进行CMP工艺以形成残留在开口内的金属互连。 然后，用等离子体处理金属互连。 等离子体处理在金属互连中产生压应力，该应力在金属互连表面产生小丘。 此外，等离子体处理工艺使得金属晶粒生长，特别是当设计规则小时，从而降低金属互连的电阻率。 然后通过CMP工艺去除小丘，目的是抛光在层间电介质层的上表面上延伸的阻挡层的部分。 最后，形成封盖绝缘层。 通过等离子体处理在金属互连的弱部分和随后的小丘的移除中有意形成小丘大大减少了在金属互连表面产生任何额外的小丘的可能性，特别是当形成覆盖层时。

公开(公告)号：US20050275005A1

公开(公告)日：2005-12-15

申请号：US11080567

申请日：2005-03-16

申请人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

发明人： Seung-Man Choi ,  Ki-Chul Park ,  Bong-Seok Suh ,  Il-Ryong Kim

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/3205 ,  H01L21/822 ,  H01L21/8234 ,  H01L23/52 ,  H01L23/522 ,  H01L27/04 ,  H01L27/108 ,  H01L29/76

CPC分类号： H01L21/76841 ,  H01L21/76846 ,  H01L21/7685 ,  H01L23/5223 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a MIM capacitor, and method of fabricating the same, the MIM capacitor includes an interlayer insulating layer on a semiconductor substrate, a lower metal interconnection and a lower metal electrode in the interlayer insulating layer, an intermetal dielectric layer covering the lower metal interconnection, the lower metal electrode, and the interlayer insulating layer, a via hole exposing the lower metal interconnection, an upper metal interconnection groove crossing over the via hole, at least one capacitor trench region exposing the lower metal electrode, an upper metal interconnection filling the upper metal interconnection groove, the upper metal interconnection being electrically connected to the lower metal interconnection through the via hole, a dielectric layer covering inner surfaces of the at least one capacitor trench region, and an upper metal electrode surrounded by the dielectric layer to fill the at least one capacitor trench region.

摘要翻译： 在MIM电容器及其制造方法中，MIM电容器包括在半导体衬底上的层间绝缘层，层间绝缘层中的下部金属互连和下部金属电极，覆盖下部金属互连的金属间介电层， 下金属电极和层间绝缘层，暴露下金属互连的通孔，与通孔相交的上金属互连槽，暴露下金属电极的至少一个电容器沟槽区，填充上金属互连的上金属互连 金属互连槽，所述上金属互连通过所述通孔电连接到所述下金属互连，覆盖所述至少一个电容器沟槽区的内表面的电介质层和被所述电介质层包围的上金属电极以填充 至少一个电容器沟槽区域。

公开(公告)号：US20050153544A1

公开(公告)日：2005-07-14

申请号：US11033189

申请日：2005-01-11

申请人： Bong-Seok Suh ,  Ki-Chul Park ,  Seung-Man Choi ,  Il-Ryong Kim

发明人： Bong-Seok Suh ,  Ki-Chul Park ,  Seung-Man Choi ,  Il-Ryong Kim

IPC分类号： H01L21/3205 ,  H01L21/285 ,  H01L21/4763 ,  H01L21/768 ,  H01L23/52

CPC分类号： H01L21/76844 ,  H01L21/2855

摘要： In a method of fabricating a semiconductor device by selectively forming a diffusion barrier layer, and a semiconductor device fabricated thereby, a conductive pattern and an insulating layer, which covers the conductive pattern, are formed on a semiconductor substrate. The insulating layer is patterned, thereby forming an opening for exposing at least a portion of the conductive pattern. Then, a diffusion barrier layer is formed on the semiconductor substrate having the opening, using a selective deposition technique. The diffusion barrier layer is formed to a thickness that is less on the exposed conductive pattern than the thickness of the diffusion barrier layer on the insulating layer exposed inside the opening. Then, the diffusion barrier layer is etched, thereby forming a recessed diffusion barrier layer. In this manner, metal atoms are prevented from being diffused from a metal plug filling the opening or a metal interconnect to the insulating layer.

摘要翻译： 在通过选择性地形成扩散阻挡层制造半导体器件的方法及其制造的半导体器件中，在半导体衬底上形成覆盖导电图案的导电图案和绝缘层。 对绝缘层进行图案化，从而形成用于暴露导电图案的至少一部分的开口。 然后，使用选择性沉积技术在具有开口的半导体衬底上形成扩散阻挡层。 扩散阻挡层形成为暴露在导体图案上的厚度小于暴露在开口内部的绝缘层上的扩散阻挡层的厚度。 然后，对扩散阻挡层进行蚀刻，从而形成凹陷扩散阻挡层。 以这种方式，防止金属原子从填充开口的金属插塞或与绝缘层的金属互连扩散。

公开(公告)号：US20050012166A1

公开(公告)日：2005-01-20

申请号：US10868360

申请日：2004-06-16

申请人： Seung-Man Choi

发明人： Seung-Man Choi

IPC分类号： H01L27/14 ,  H01L27/146

CPC分类号： H01L27/14625 ,  H01L27/14621 ,  H01L27/14636 ,  H01L27/14683 ,  H01L27/14685

摘要： In an image sensor device, an insulating interlayer structure having an opening is formed on a semiconductor substrate on which a semiconductor device and a photodetector are formed. An electrically conductive pattern, e.g, copper, fills the opening. A diffusion preventing pattern is formed only on the electrically conductive pattern. A color filter and a lens are also provided in an optical path of the photodetector. The diffusion preventing pattern is not disposed in the optical path of the photodetector. Thus, the image sensor device having the copper pattern may be easily manufactured.

摘要翻译： 在图像传感器装置中，在形成有半导体器件和光电检测器的半导体衬底上形成具有开口的绝缘层间结构。 诸如铜的导电图案填充开口。 仅在导电图案上形成扩散防止图案。 滤光器和透镜也设置在光电检测器的光路中。 扩散防止图案不设置在光电检测器的光路中。 因此，可以容易地制造具有铜图案的图像传感器装置。

公开(公告)号：US20110163387A1

公开(公告)日：2011-07-07

申请号：US13050219

申请日：2011-03-17

申请人： Kyoung Woo Lee ,  Ja Hum Ku ,  Taehoon Lee ,  Seung-Man Choi ,  Thomas W. Dyer

发明人： Kyoung Woo Lee ,  Ja Hum Ku ,  Taehoon Lee ,  Seung-Man Choi ,  Thomas W. Dyer

IPC分类号： H01L27/092

CPC分类号： H01L21/823807 ,  H01L21/823871 ,  H01L29/7843

摘要： CMOS (complementary metal oxide semiconductor) fabrication techniques are provided to form DSL (dual stress liner) semiconductor devices having non-overlapping, self-aligned, dual stress liner structures.

摘要翻译： 提供CMOS（互补金属氧化物半导体）制造技术以形成具有非重叠，自对准的双应力衬垫结构的DSL（双应力衬垫）半导体器件。

公开(公告)号：US20090128740A1

公开(公告)日：2009-05-21

申请号：US12289636

申请日：2008-10-31

申请人： Kyung Joon Lee ,  Seung Man Choi ,  Man Suk Kim

发明人： Kyung Joon Lee ,  Seung Man Choi ,  Man Suk Kim

IPC分类号： G02F1/1335 ,  F21V11/00

CPC分类号： G02F1/133611 ,  G02F1/133604 ,  G02F1/133606 ,  G02F2001/133607

摘要： A diffuser plate includes a first optical sheet having a rear surface configured to receive light from a light source and having a front surface configured to provide light to a second optical sheet, the first optical sheet having a refractive part that includes a plurality of optical members at a surface of the first optical sheet, and a second optical sheet disposed in front of the first optical sheet, the second optical sheet including a rear surface configured to receive light from the first optical sheet, a front surface configured to emit light, and light-scattering beads within the first optical sheet.

摘要翻译： 扩散板包括第一光学片，其具有被配置为接收来自光源的光并且具有被配置为向第二光学片提供光的前表面的后表面，所述第一光学片具有折射部分，所述折射部分包括多个光学部件 在第一光学片的表面和设置在第一光学片的前方的第二光学片，第二光学片包括被配置为接收来自第一光学片的光的后表面，被配置为发光的前表面，以及 第一光学片内的光散射珠。

公开(公告)号：US07417302B2

公开(公告)日：2008-08-26

申请号：US11174864

申请日：2005-07-05

申请人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

发明人： Kyoung-Woo Lee ,  Hong-Jae Shin ,  Jeong-Hoon Ahn ,  Seung-Man Choi ,  Byung-Jun Oh ,  Yoon-Hae Kim

IPC分类号： H01L29/00

CPC分类号： H01L23/5223 ,  H01L21/76808 ,  H01L21/76877 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

摘要： In a method of manufacturing a semiconductor device, a first insulation layer on the substrate is patterned to form a first opening having a first width. A lower electrode is formed along an inner contour of the first opening. A second insulation layer on the first insulation layer is patterned to form a second opening that has a second width greater than the first width and is connected to the first opening with a stepped portion. A dielectric layer is formed on the lower electrode in the first opening, a sidewall of the second opening and a first stepped portion between the first insulation layer and the second insulation layer, so that the electrode layer is covered with the dielectric layer. An upper electrode is formed on the dielectric layer. Accordingly, a leakage current between the lower and upper electrodes is suppressed.

摘要翻译： 在制造半导体器件的方法中，将衬底上的第一绝缘层图案化以形成具有第一宽度的第一开口。 沿着第一开口的内轮廓形成下电极。 第一绝缘层上的第二绝缘层被图案化以形成具有大于第一宽度的第二宽度的第二开口，并且连接到具有台阶部分的第一开口。 在第一开口的下电极，第二开口的侧壁和第一绝缘层与第二绝缘层之间的第一台阶部分上形成电介质层，使电极层被电介质层覆盖。 在电介质层上形成上电极。 因此，抑制了下电极和上电极之间的漏电流。

公开(公告)号：US20080008845A1

公开(公告)日：2008-01-10

申请号：US11822049

申请日：2007-07-02

申请人： Young Oh ,  Chang Hee Cho ,  Seung Man Choi

发明人： Young Oh ,  Chang Hee Cho ,  Seung Man Choi

IPC分类号： B32B27/28 ,  B32B27/08 ,  B32B3/00

CPC分类号： C08J7/042 ,  C08J7/047 ,  C08J2425/00 ,  Y10T428/1036 ,  Y10T428/24628 ,  Y10T428/26 ,  Y10T428/269 ,  Y10T428/3175 ,  Y10T428/31797 ,  Y10T428/31855

摘要： A light diffusion sheet for a display device includes a base layer having a base resin mixture of a methacrylate-styrene copolymer and a methylmethacrylate-styrene copolymer and about 0.2 to 20 ppwb of a first light diffuser, and at least one coating layer on the base layer, the coating layer including a methylmethacrylate-styrene copolymer base coating resin, about 0.1 to 30 ppwb of a second light diffuser, about 0.01 to 2 ppwb of an UV absorber, and about 0.001 to 10 ppwb of an antistatic agent.

摘要翻译： 用于显示装置的光漫射片包括具有甲基丙烯酸酯 - 苯乙烯共聚物和甲基丙烯酸甲酯 - 苯乙烯共聚物的基础树脂混合物和约0.2至20ppwb的第一光漫射体的基底层和在基底上的至少一个涂层 层，包括甲基丙烯酸甲酯 - 苯乙烯共聚物基涂层树脂的涂层，约0.1至30ppwb的第二光漫射体，约0.01至2ppwb的UV吸收剂和约0.001至10ppwb的抗静电剂。

公开(公告)号：US07586175B2

公开(公告)日：2009-09-08

申请号：US11551864

申请日：2006-10-23

申请人： Kyoung Woo Lee ,  Ja Hum Ku ,  Ki Chul Park ,  Seung Man Choi

发明人： Kyoung Woo Lee ,  Ja Hum Ku ,  Ki Chul Park ,  Seung Man Choi

IPC分类号： H01L23/544 ,  H01L21/4763

CPC分类号： H01L23/53238 ,  H01L21/2885 ,  H01L23/564 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor wafer having multi-layer metallization structures that are fabricated to include embedded interconnection structures which serve as low-resistance electroplating current paths to conduct bulk electroplating current fed to portions of a metallic seed layer at peripheral surface regions of the wafer to portions of the metallic seed layer at inner/central surface regions of the semiconductor wafer to achieve uniformity in metal plating in chip regions across the wafer.

摘要翻译： 具有多层金属化结构的半导体晶片，其被制造为包括用作低电阻电镀电流路径的嵌入式互连结构，以将在晶片的外围表面区域处的金属种子层的部分进料的体电镀电流传导到 金属种子层在半导体晶片的内/中心表面区域，以实现跨晶片的芯片区域中金属电镀的均匀性。