公开(公告)号：US08587036B2

公开(公告)日：2013-11-19

申请号：US12333315

申请日：2008-12-12

申请人： Shih-Chen Wang ,  Wen-Hao Ching

发明人： Shih-Chen Wang ,  Wen-Hao Ching

IPC分类号： H01L29/788

CPC分类号： H01L27/11558 ,  H01L27/11517 ,  H01L27/11519

摘要： A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.

摘要翻译： 在基板上形成非易失性存储器。 非易失性存储器包括隔离结构，浮动栅极和栅极电介质层。 隔离结构设置在基板中以限定有源区域。 浮动栅极设置在基板上并且跨过有效区域。 栅极电介质层设置在浮置栅极和衬底之间。 浮动栅极包括第一区域和第二区域。 第二区域的能带低于第一区域的能带，使得存储在浮置栅极中的电荷远离浮置栅极和栅极电介质层的重叠区域。

公开(公告)号：US08456916B2

公开(公告)日：2013-06-04

申请号：US13541755

申请日：2012-07-04

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Wen-Hao Ching ,  Yen-Hsin Lai ,  Hau-Yan Lu ,  Ching-Sung Yang

IPC分类号： G11C11/34

CPC分类号： H01L27/088 ,  G11C16/0458 ,  G11C16/28 ,  G11C16/3418

摘要： An only-one-polysilicon layer non-volatile memory unit cell includes a first P-type transistor, a second P-type transistor, a N-type transistor pair, a first and second coupling capacitors is provided. The N-type transistor pair has a third transistor and a fourth transistor that are connected. The third transistor and the fourth transistor have a first floating polysilicon gate and a second floating polysilicon gate to serve as charge storage mediums, respectively. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage. One end of the second coupling capacitor is connected to the gate of the second transistor and is coupled to the second floating polysilicon gate, the other end of the second coupling capacitor receives a second control voltage.

摘要翻译： 唯一一多晶硅层非易失性存储单元包括第一P型晶体管，第二P型晶体管，N型晶体管对，第一和第二耦合电容器。 N型晶体管对具有连接的第三晶体管和第四晶体管。 第三晶体管和第四晶体管分别具有第一浮置多晶硅栅极和第二浮置多晶硅栅极，用作电荷存储介质。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。 第二耦合电容器的一端连接到第二晶体管的栅极并且耦合到第二浮置多晶硅栅极，第二耦合电容器的另一端接收第二控制电压。

公开(公告)号：US08339831B2

公开(公告)日：2012-12-25

申请号：US12899562

申请日：2010-10-07

申请人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

发明人： Hau-Yan Lu ,  Ching-Sung Yang ,  Shih-Chen Wang ,  Hsin-Ming Chen

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18

摘要： A one-time-programmable memory device comprises a one-time-programmable memory cell array, a voltage pumping circuit, and a programming verification circuit. The one-time-programmable memory cell array comprises a plurality of memory cells. Each memory cell is arranged at an intersection of a bit line and a word line. The voltage pumping circuit comprises a plurality of local voltage boost circuits. Each local voltage boost circuit is shared by a corresponding memory cell of the plurality of memory cells. The programming verification circuit is coupled to the one-time-programmable memory cell array for verifying that conduction current of programmed memory cells of the plurality of memory cells is greater than a predetermined current level after programming. Each local boost circuit isolates leakage current of a corresponding programmed memory cell, and prevents programming voltage failure due to current overloading at a corresponding voltage pumping circuit.

摘要翻译： 一次可编程存储器件包括一次可编程存储器单元阵列，电压泵浦电路和编程验证电路。 一次可编程存储单元阵列包括多个存储单元。 每个存储单元被布置在位线和字线的交点处。 电压泵浦电路包括多个局部升压电路。 每个本地升压电路由多个存储单元的相应存储单元共享。 编程验证电路耦合到一次可编程存储单元阵列，用于在编程之后验证多个存储单元的编程存储单元的传导电流大于预定电流电平。 每个本地升压电路隔离相应的编程存储单元的漏电流，并且防止由于在相应的电压泵浦电路处的电流过载导致的编程电压故障。

公开(公告)号：US20120314474A1

公开(公告)日：2012-12-13

申请号：US13157295

申请日：2011-06-09

申请人： Hsin-Ming Chen ,  Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hsin-Ming Chen ,  Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： G11C17/18 ,  H01L27/12

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L21/84 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/1203

摘要： The present invention provides a non-volatile memory cell structure. A first isolation structure is disposed on a substrate and a semiconductor layer is disposed on the first isolation structure to form a silicon on insulator device. A first doping region is made of a portion of the semiconductor layer. A gate is disposed on the first doping region. A gate oxide layer is sandwiched between the first doping region and the gate. A second doping region is disposed within the semiconductor layer and outside the first doping region. A second doping region is in direct contact with the first doping region. A second isolation structure is disposed on the first isolation structure. Further, the second isolation structure surrounds the first doping region and the second doping region. The second isolation structure is also in direct contact with the first doping region and the second doping region.

摘要翻译： 本发明提供一种非易失性存储单元结构。 第一隔离结构设置在衬底上，半导体层设置在第一隔离结构上以形成绝缘体上硅器件。 第一掺杂区域由半导体层的一部分制成。 栅极设置在第一掺杂区域上。 栅极氧化层夹在第一掺杂区域和栅极之间。 第二掺杂区域设置在半导体层内并且在第一掺杂区域的外部。 第二掺杂区域与第一掺杂区域直接接触。 第二隔离结构设置在第一隔离结构上。 此外，第二隔离结构围绕第一掺杂区域和第二掺杂区域。 第二隔离结构也与第一掺杂区和第二掺杂区直接接触。

公开(公告)号：US08174063B2

公开(公告)日：2012-05-08

申请号：US12633780

申请日：2009-12-08

申请人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Hau-Yan Lu ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： H01L29/788

CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42344

摘要： A non-volatile semiconductor memory device includes a substrate, a first gate formed on a first region of a surface of the substrate, a second gate formed on a second region of the surface of the substrate, a charge storage layer filled between the first gate and the second gate, a first diffusion region formed on a first side of the charge storage layer, and a second diffusion region formed opposite the charge storage layer from the first diffusion region. The first region and the second region are separated by a distance sufficient for forming a self-aligning charge storage layer therebetween.

摘要翻译： 非挥发性半导体存储器件包括：衬底;形成在衬底表面的第一区域上的第一栅极;形成在衬底表面的第二区域上的第二栅极;填充在第一栅极之间的电荷存储层; 并且所述第二栅极，形成在所述电荷存储层的第一侧上的第一扩散区域和与所述第一扩散区域形成在与所述电荷存储层相对的第二扩散区域。 第一区域和第二区域被分开足以在其之间形成自对准电荷存储层的距离。

公开(公告)号：US08089798B2

公开(公告)日：2012-01-03

申请号：US12627244

申请日：2009-11-30

申请人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

发明人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

IPC分类号： G11C17/00

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206

摘要： A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

摘要翻译： 提供了一种用于操作一次性可编程只读存储器（OTP-ROM）的方法。 OTP-ROM包括分别设置在衬底上的第一掺杂区域和第二掺杂区域之间的栅极电介质层上的第一栅极和第二栅极，其中第一栅极与第一掺杂区域相邻并耦合到第一掺杂区域 所述第二栅极与所述第二掺杂区相邻，所述第一栅极电耦合接地，并且通过击穿效应对所述OTP-ROM进行编程。 该方法包括在第二掺杂区域的电压高于第一掺杂区域的电压的条件下对OTP-ROM进行编程的步骤，第二栅极的电压高于阈值电压以通过 第二掺杂区域和第一掺杂区域和衬底处于参考电压。

公开(公告)号：US20110310669A1

公开(公告)日：2011-12-22

申请号：US12818095

申请日：2010-06-17

申请人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

发明人： Wen-Hao Ching ,  Shih-Chen Wang ,  Ching-Sung Yang

IPC分类号： G11C16/04

CPC分类号： G11C16/0441 ,  G11C2216/10 ,  H01L27/11519 ,  H01L27/11524 ,  H01L29/66825 ,  H01L29/7881

摘要： A non-volatile memory system includes one or more non-volatile memory cells. Each non-volatile memory cell comprises a floating gate, a coupling device, a first floating gate transistor, and a second floating gate transistor. The coupling device is located in a first conductivity region. The first floating gate transistor is located in a second conductivity region, and supplies read current sensed during a read operation. The second floating gate transistor is located in a third conductivity region. Such non-volatile memory cell further comprises two transistors for injecting negative charge into the floating gate during a programming operation, and removing negative charge from the second floating gate transistor during an erase operation. The floating gate is shared by the first floating gate transistor, the coupling device, and the second floating gate transistor, and extends over active regions of the first floating gate transistor, the coupling device and the second floating gate transistor.

摘要翻译： 非易失性存储器系统包括一个或多个非易失性存储器单元。 每个非易失性存储单元包括浮动栅极，耦合器件，第一浮栅晶体管和第二浮栅晶体管。 耦合装置位于第一导电区域中。 第一浮栅晶体管位于第二导电区域中，并提供在读操作期间感测到的读电流。 第二浮栅晶体管位于第三导电区域中。 这种非易失性存储单元还包括两个晶体管，用于在编程操作期间将负电荷注入浮置栅极，以及在擦除操作期间从第二浮栅晶体管去除负电荷。 浮置栅极由第一浮栅晶体管，耦合器件和第二浮栅晶体管共享，并且延伸在第一浮栅晶体管，耦合器件和第二浮栅晶体管的有源区上。

公开(公告)号：US07768059B2

公开(公告)日：2010-08-03

申请号：US11690861

申请日：2007-03-26

申请人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

发明人： Hsin-Ming Chen ,  Shih-Chen Wang ,  Ming-Chou Ho ,  Shih-Jye Shen

IPC分类号： H01L29/788

CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11558

摘要： A non-volatile single-poly memory device is disclosed. The non-volatile single-poly memory device includes two mirror symmetric unit cells, which is capable of providing improved data correctness. Further, the non-volatile single-poly memory device is operated at low voltages and is fully compatible with logic processes.

摘要翻译： 公开了一种非易失性单多晶硅存储器件。 非易失性单多晶硅存储器件包括两个镜像对称单元单元，其能够提供改进的数据正确性。 此外，非易失性单多晶硅存储器件在低电压下操作并且与逻辑工艺完全兼容。

公开(公告)号：US20100148238A1

公开(公告)日：2010-06-17

申请号：US12333315

申请日：2008-12-12

申请人： Shih-Chen Wang ,  Wen-Hao Ching

发明人： Shih-Chen Wang ,  Wen-Hao Ching

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11558 ,  H01L27/11517 ,  H01L27/11519

摘要： A non-volatile memory is formed on a substrate. The non-volatile memory includes an isolation structure, a floating gate, and a gate dielectric layer. The isolation structure is disposed in the substrate to define an active area. The floating gate is disposed on the substrate and crosses over the active area. The gate dielectric layer is disposed between the floating gate and the substrate. The floating gate includes a first region and a second region. An energy band of the second region is lower than an energy band of the first region, so that charges stored in the floating gate are away from an overlap region of the floating gate and the gate dielectric layer.

摘要翻译： 在基板上形成非易失性存储器。 非易失性存储器包括隔离结构，浮动栅极和栅极电介质层。 隔离结构设置在基板中以限定有源区域。 浮动栅极设置在基板上并且跨越有效区域。 栅极电介质层设置在浮置栅极和衬底之间。 浮动栅极包括第一区域和第二区域。 第二区域的能带低于第一区域的能带，使得存储在浮置栅极中的电荷远离浮置栅极和栅极电介质层的重叠区域。

公开(公告)号：US20100073985A1

公开(公告)日：2010-03-25

申请号：US12627244

申请日：2009-11-30

申请人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

发明人： Tsung-Mu Lai ,  Shao-Chang Huang ,  Wen-hao Ching ,  Chun-Hung Lu ,  Shih-Chen Wang ,  Ming-Chou Ho

IPC分类号： G11C17/08

CPC分类号： H01L27/112 ,  G11C17/16 ,  G11C17/18 ,  H01L27/11206

摘要： A method for operating a one-time programmable read-only memory (OTP-ROM) is provided. The OTP-ROM comprises a first gate and a second gate respectively disposed on a gate dielectric layer between a first doped region and a second doped region on a substrate, wherein the first gate is adjacent to the first doped region and coupled to the first doped region, the second gate is adjacent to the second doped region, the first gate is electrically coupled grounded, and the OTP-ROM is programmed through a breakdown effect. The method comprises a step of programming the OTP-ROM under the conditions that a voltage of the second doped region is higher than a voltage of the first doped region, the voltage of the second gate is higher than a threshold voltage to pass the voltage of the second doped region, and the first doped region and the substrate are at a reference voltage.

摘要翻译： 提供了一种用于操作一次性可编程只读存储器（OTP-ROM）的方法。 OTP-ROM包括分别设置在衬底上的第一掺杂区域和第二掺杂区域之间的栅极电介质层上的第一栅极和第二栅极，其中第一栅极与第一掺杂区域相邻并耦合到第一掺杂区域 所述第二栅极与所述第二掺杂区相邻，所述第一栅极电耦合接地，并且通过击穿效应对所述OTP-ROM进行编程。 该方法包括在第二掺杂区域的电压高于第一掺杂区域的电压的条件下对OTP-ROM进行编程的步骤，第二栅极的电压高于阈值电压以通过 第二掺杂区域和第一掺杂区域和衬底处于参考电压。