公开(公告)号：US20080211060A1

公开(公告)日：2008-09-04

申请号：US11680630

申请日：2007-03-01

Applicant: Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung-Jen Ho

Inventor： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung-Jen Ho

IPC: H01L29/72

CPC classification number: H01L23/5252 ,  H01L27/101 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An anti-fuse is formed with a transistor with a doped channel. The anti-fuse will not generate a non-linear current after the anti-fuse is blown. The anti-fuse is used in memory cells of one-time programmable (OTP) memory. The OTP memory utilizes a p-type transistor and an n-type transistor to program the anti-fuse. The anti-fuse has the doped channel, so a current will not flow through the p/n junction between the substrate and two doped regions of the anti-fuse to form a non-linear current after the anti-fuse is blown. Thus, the memory cells of the OTP memory can be programmed correctly.

Abstract translation: 用具有掺杂沟道的晶体管形成反熔丝。 反熔丝熔断后，反熔丝不会产生非线性电流。 反熔丝用于一次可编程（OTP）存储器的存储单元。 OTP存储器利用p型晶体管和n型晶体管编程反熔丝。 反熔丝具有掺杂沟道，因此在抗熔丝被熔断之后，电流将不会流过衬底和反熔丝的两个掺杂区之间的p / n结，以形成非线性电流。 因此，可以正确编程OTP存储器的存储单元。

公开(公告)号：US06380587B1

公开(公告)日：2002-04-30

申请号：US09706527

申请日：2000-11-03

Applicant: Shing-Ren Sheu ,  Chung-Hsien Wu ,  Chih-Ming Huang

Inventor： Shing-Ren Sheu ,  Chung-Hsien Wu ,  Chih-Ming Huang

IPC: H01L2976

CPC classification number: H01L27/1126 ,  H01L27/105 ,  H01L27/11293

Abstract: A semiconductor read-only memory (ROM) and a method of fabricating the same are provided. The ROM device is structured in such a manner that allows the fabrication to include a fewer number of mask processes. This makes it more cost effective and allows a cycle time that is shorter than that of the prior art. Moreover, the particular structure of the ROM device makes punchthrough less likely to occur between any neighboring pairs of the buried bit lines when the ROM device is further scaled down. The ROM device is constructed on a semiconductor substrate which is partitioned into a peripheral region and a cell region. A plurality of STI structures are formed at predefined locations in both the peripheral region and the cell region. Immediately after this, a first ion-implantation process can be performed on the cell region to form a plurality of buried bit lines. Subsequently, the dielectric isolation layers in all of the STI structures in the cell region are removed, leaving a plurality of empty trenches behind. A conformal insulating layer and a conductive layer are then successively formed over the wafer, and the conductive layer is further selectively removed to form a word line in the cell region and a gate in the peripheral region. In the code implantation process, selected channel regions between the buried bit lines are doped with impurities for code implantation of data into the ROM device.

公开(公告)号：US6146950A

公开(公告)日：2000-11-14

申请号：US389722

申请日：1999-09-03

Applicant: Shing-Ren Sheu ,  Chin-Lung Chen ,  Tzyy-Jye Lin

Inventor： Shing-Ren Sheu ,  Chin-Lung Chen ,  Tzyy-Jye Lin

IPC: H01L21/8246

CPC classification number: H01L27/11293

Abstract: A method of manufacturing multiple metallic layered embedded ROM. A substrate has a memory cell region and a peripheral circuit region. A first gate and a first source/drain region are formed in the memory cell region. A second gate and a second source/drain region are formed in the peripheral circuit region. A first dielectric layer is formed over the substrate. A first contact is formed in the first dielectric layer in the periphery circuit region. A first patterned metallic layer that couple electrically with the first contact is formed in the peripheral circuit region. A second dielectric layer is formed over the substrate. A portion of the second dielectric layer in the memory cell region is removed to form a remaining second dielectric layer having a sloping sidewall surrounds a periphery of the memory cell region. A via hole is formed in the second dielectric layer in the peripheral circuit region and a second contact opening is formed in the first dielectric layer in the memory cell region. The via hole exposes the first patterned metallic layer. A metallic barrier layer is formed over the substrate. Ions are implanted into coded regions in the substrate. A second patterned metallic layer is formed in the peripheral circuit region to cover the second dielectric layer and fill the via hole. A third patterned metallic layer is formed in the memory cell region to fill the contact opening. A passivation layer is formed over the substrate.

Abstract translation: 一种制造多金属分层嵌入式ROM的方法。 衬底具有存储单元区域和外围电路区域。 第一栅极和第一源极/漏极区域形成在存储单元区域中。 第二栅极和第二源极/漏极区域形成在外围电路区域中。 第一电介质层形成在衬底上。 在外围电路区域中的第一电介质层中形成第一接触。 在外围电路区域中形成有与第一接触电连接的第一图案化金属层。 第二介质层形成在衬底上。 去除存储单元区域中的第二电介质层的一部分以形成具有围绕存储单元区域周边的倾斜侧壁的剩余第二电介质层。 在外围电路区域中的第二电介质层中形成通孔，并且在存储单元区域中的第一电介质层中形成第二接触开口。 通孔露出第一图案化金属层。 在衬底上形成金属阻挡层。 离子植入衬底中的编码区域。 第二图案化金属层形成在外围电路区域中以覆盖第二电介质层并填充通孔。 在存储单元区域中形成第三图案化金属层以填充接触开口。 钝化层形成在衬底上。

公开(公告)号：US6093626A

公开(公告)日：2000-07-25

申请号：US897229

申请日：1997-07-29

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/02 ,  H01L21/331 ,  H01L21/22 ,  H01L21/26

CPC classification number: H01L27/0255

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract translation: 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

公开(公告)号：US5998832A

公开(公告)日：1999-12-07

申请号：US955872

申请日：1997-10-22

Applicant: Shing-Ren Sheu ,  Chung-Yuan Lee

Inventor： Shing-Ren Sheu ,  Chung-Yuan Lee

IPC: H01L21/336 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L29/66568 ,  H01L27/0251 ,  H01L27/0266

Abstract: An improved metal oxide field effect transistor (MOSFET) provides an electro-static protection device with a high resistance to electro-static discharge. The electro-static discharge protection device has pre-gate heavily doped regions adjacent to the source and drain regions, where the pre-gate regions extend at least partially under the gate electrode. A single heavily doped pre-gate region may be provided for the MOSFET of the electro-static discharge protection circuit.

Abstract translation: 改进的金属氧化物场效应晶体管（MOSFET）提供了具有高静电放电电阻的静电保护装置。 静电放电保护器件具有与源极和漏极区域相邻的预栅极重掺杂区域，其中预栅极区域至少部分地延伸到栅电极下方。 可以为静电放电保护电路的MOSFET提供单个重掺杂的预栅极区域。

公开(公告)号：US5654576A

公开(公告)日：1997-08-05

申请号：US559324

申请日：1995-11-16

Applicant: Chen-Chiu Hsue ,  Yi-Chung Sheng ,  Shing-Ren Sheu ,  Chen-Hui Chung

Inventor： Chen-Chiu Hsue ,  Yi-Chung Sheng ,  Shing-Ren Sheu ,  Chen-Hui Chung

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/94

CPC classification number: H01L27/1126 ,  H01L27/112 ,  Y10S257/915

Abstract: A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.

Abstract translation: 一种在半导体衬底上制造具有与其一体的基本上平行的掩埋位线阵列和掩埋位线之上的字线的阵列的方法，包括：在字线之上形成氮化钛层，形成码图掩模 在氮化钛层之上，通过编码掩模中的开口将杂质注入到衬底中，以形成编码图案，并对植入物进行快速热退火。 氮化钛层的台阶高度用于在基板上形成代码识别。