公开(公告)号：US5576573A

公开(公告)日：1996-11-19

申请号：US454701

申请日：1995-05-31

申请人： Kuan-Cheng Su ,  Shing-Ren Sheu

发明人： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC分类号： H01L27/112 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/112 ,  H01L29/42368 ,  Y10S438/981

摘要： A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

摘要翻译： 一种用于掩模ROM器件的多状态存储单元。 源极/漏极区域沿着衬底和位线的平面上沿着第一方向延伸的条带布置在衬底上。 栅极氧化物层沿着第二方向布置在基板上。 栅极电极分别形成在每个栅极氧化物层的顶部上，作为沿第二方向延伸的条带。 栅极氧化物层具有多个选定的厚度，以差分系列排列。 每个晶体管沟道区以及它们相应的一个源极/漏极对，顶部的栅极氧化物层和进一步在其顶部的栅电极构成一个存储单元，其可以使其阈值电压在 差分系列的厚度允许存储用于存储器单元的多位等效的存储器内容。

公开(公告)号：US5691234A

公开(公告)日：1997-11-25

申请号：US511065

申请日：1995-08-03

申请人： Kuan-Cheng Su ,  Shing-Ren Sheu

发明人： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC分类号： H01L27/02 ,  H01L21/28

CPC分类号： H01L27/0255

摘要： A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

摘要翻译： 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

公开(公告)号：US5597753A

公开(公告)日：1997-01-28

申请号：US364318

申请日：1994-12-27

申请人： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

发明人： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

IPC分类号： H01L21/8246

CPC分类号： H01L27/11246 ,  Y10S438/981

摘要： An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line. The elimination of the implant also reduces substantially the stand-by leakage current that is so important in battery operated electronic equipment, such as lap-top computers. The gate capacitance of the off-state cells is also substantially reduced because of the thick insulating layer, thereby reducing the RC time delay in the word lines and improving circuit performance.

摘要翻译： 实现了改进的只读存储器（ROM）结构和制造具有超高密度编码ROM单元的所述ROM器件结构的方法。 编程ROM单元的阵列由每个ROM单元中的单个场效应晶体管（FET）构成。 改进的ROM处理利用在施加栅极电压时选择为保持在截止状态（非导通）的每个编码的FET（单元）上的ROM代码绝缘层的图案化。 当施加栅极电压时，剩余的FET（单元）具有薄的栅极氧化物，其切换到导通状态（导通）。 粗ROM代码绝缘层消除了通过常规高剂量离子注入对ROM存储单元中的FET进行编码的需要。 这通过注入消除了掩埋位线的反掺杂，允许掩埋位线之间的间隔更紧密的基本规则。 植入物的消除也大大降低了备用泄漏电流，这在电池供电的电子设备如笔记本电脑中如此重要。 由于厚的绝缘层，断态单元的栅极电容也显着减小，从而减小了字线中的RC时间延迟并提高了电路性能。

公开(公告)号：US5382534A

公开(公告)日：1995-01-17

申请号：US254534

申请日：1994-06-06

申请人： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung

发明人： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung

IPC分类号： H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265

CPC分类号： H01L29/66636 ,  H01L29/0847 ,  H01L29/1083

摘要： The invention describes recessed buried conductive regions formed in a trench in the substrate that provides a smooth surface topology, smaller devices and improved device performance. The buried regions have two conductive regions, the first on the trench sidewalls, the second on the trench bottom. In addition, two buried layers are formed between adjacent buried conductive regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the conductive regions on the trench bottoms. The first conductive region and the anti-punchthrough layer have the effect of increasing the punchthru voltage without increasing the threshold voltage. The first and second regions also lowers the resistivity of the buried regions allowing use of smaller line pitches and therefore smaller devices. Overall, the recessed conductive regions and the two buried layers allow the formation of smaller devices with improved performance.

摘要翻译： 本发明描述了形成在衬底中的沟槽中的凹入的埋入导电区域，其提供了平滑的表面拓扑，较小的器件和改进的器件性能。 掩埋区域具有两个导电区域，第一个在沟槽侧壁上，第二个在沟槽底部。 此外，在相邻的掩埋导电区域之间形成两个掩埋层：在衬底表面附近的阈值电压层和形成在与沟槽底部上的导电区域大致相同深度的抗穿通层。 第一导电区域和抗穿通层具有增加穿透电压而不增加阈值电压的效果。 第一和第二区域也降低了掩埋区域的电阻率，从而允许使用较小的线间距并因此使用较小的器件。 总的来说，凹入的导电区域和两个掩埋层允许形成具有改进的性能的较小的器件。

公开(公告)号：US6093626A

公开(公告)日：2000-07-25

申请号：US897229

申请日：1997-07-29

申请人： Kuan-Cheng Su ,  Shing-Ren Sheu

发明人： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC分类号： H01L27/02 ,  H01L21/331 ,  H01L21/22 ,  H01L21/26

CPC分类号： H01L27/0255

摘要： A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

摘要翻译： 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

公开(公告)号：US20090026576A1

公开(公告)日：2009-01-29

申请号：US11782154

申请日：2007-07-24

申请人： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

发明人： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

IPC分类号： H01L29/00 ,  H01L21/336

CPC分类号： H01L23/5252 ,  H01L21/26586 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse is provided. The anti-fuse includes a substrate, a gate disposed over the substrate, a gate dielectric layer sandwiched between the substrate and the gate, and two source/drain regions in the substrate at respective sides of the gate. The gate and the substrate have the same conductive type, but the conductive type of the gate and the substrate is different from that of the two source/drain regions.

摘要翻译： 提供反熔丝。 反熔丝包括衬底，设置在衬底上的栅极，夹在衬底和栅极之间的栅极电介质层以及在栅极的相应侧的衬底中的两个源极/漏极区域。 栅极和衬底具有相同的导电类型，但是栅极和衬底的导电类型与两个源极/漏极区的导电类型不同。

公开(公告)号：US5942786A

公开(公告)日：1999-08-24

申请号：US767824

申请日：1996-12-17

申请人： Shing-Ren Sheu ,  Cheng-Chih Kung

发明人： Shing-Ren Sheu ,  Cheng-Chih Kung

IPC分类号： H01L27/112 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/112

摘要： A mask ROM stores information by selecting the work function of the gates of each FET in an array of FETs. The polysilicon gates of some of the FETs are doped N-type and the gates of the other FETs are doped P-type to form gates having different work functions, thereby forming FETs having different threshold voltages. The ROM consists of a parallel array of buried N.sup.+ bit lines formed in the substrate, a gate oxide layer deposited over the bit lines and a layer of polysilicon deposited on the gate oxide. The polysilicon is blanket doped P-type and then an encoding mask is formed, with openings in the encoding mask exposing regions of the polysilicon to be formed into gates of FETs with low threshold voltages. Either arsenic or phosphorus is doped into the polysilicon through the mask openings. The mask is removed, a layer of conductive material such as tungsten silicide is deposited and the polysilicon and the conductive material are formed into word lines for the ROM. The word lines of the ROM serve as gates for the FETs and the bit lines serve as sources and drains for the FETs.

公开(公告)号：US20090322360A1

公开(公告)日：2009-12-31

申请号：US12145518

申请日：2008-06-25

申请人： Shing-Ren Sheu ,  Chun-Chieh Huang

发明人： Shing-Ren Sheu ,  Chun-Chieh Huang

IPC分类号： G01R31/28

CPC分类号： G01R31/2884 ,  G01R31/2831

摘要： A test system provides defect information rapidly and systematically. The test system includes a plurality of test units arranged in a matrix, a plurality of bit lines and a plurality of word lines. Each test unit has a first terminal and a second terminal. Each second terminal of the test unit is electrically connected to a ground point. The first terminals of the test units are electrically connected to the bit lines. The word lines are coupled to the test units. Defects in the each test unit can be identified by providing voltages to the bit lines and the word lines. Accordingly, defects in various devices of an integrated circuit can be detected rapidly and systematically by applying signals to the test system.

摘要翻译： 测试系统快速有系统地提供缺陷信息。 测试系统包括以矩阵，多个位线和多个字线布置的多个测试单元。 每个测试单元具有第一端子和第二端子。 测试单元的每个第二端子电连接到接地点。 测试单元的第一个端子电连接到位线。 字线耦合到测试单元。 可以通过向位线和字线提供电压来识别每个测试单元中的缺陷。 因此，可以通过向测试系统施加信号来快速且系统地检测集成电路的各种装置中的缺陷。

公开(公告)号：US20090029541A1

公开(公告)日：2009-01-29

申请号：US12211608

申请日：2008-09-16

申请人： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

发明人： Kuang-Yeh Chang ,  Shing-Ren Sheu ,  Chung Jen Ho

IPC分类号： H01L21/44

CPC分类号： H01L23/5252 ,  H01L21/26586 ,  H01L27/115 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of fabricating an anti-fuse includes firstly forming a dielectric layer on a substrate having a first conductive type. Next, a conductive layer is formed on the dielectric layer. A first ion implantation process is then performed, such that the conductive layer has the first conductive type. Thereafter, the conductive layer and the dielectric layer are patterned to form a gate and a gate dielectric layer. The gate and the gate dielectric layer together construct a gate structure. Finally, two source/drain regions having a second conductive type are formed in the substrate at respective sides of the gate. Besides, a method of programming an anti-fuse includes firstly applying a voltage to a gate to break down a gate dielectric layer. The gate and a substrate are then electrically conducted or a P/N forward bias is then formed in a P/N junction after the breakdown of the gate dielectric layer.

摘要翻译： 制造抗熔丝的方法包括首先在具有第一导电类型的衬底上形成电介质层。 接下来，在电介质层上形成导电层。 然后执行第一离子注入工艺，使得导电层具有第一导电类型。 此后，对导电层和电介质层进行构图以形成栅极和栅极电介质层。 栅极和栅极电介质层一起构成栅极结构。 最后，具有第二导电类型的两个源极/漏极区域形成在栅极的相应侧的衬底中。 此外，编制反熔丝的方法包括首先向栅极施加电压以分解栅极电介质层。 然后对栅极和衬底进行电导或在栅极电介质层击穿之后在P / N结中形成P / N正向偏压。

公开(公告)号：US07026234B2

公开(公告)日：2006-04-11

申请号：US10709940

申请日：2004-06-08

申请人： Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

发明人： Jui-Meng Jao ,  Shing-Ren Sheu ,  Kuo-Ming Chen ,  Hung-Min Liu ,  Kun-Chih Wang

IPC分类号： H01L21/44 ,  H01L29/40

CPC分类号： H01L24/13 ,  H01L23/5222 ,  H01L24/11 ,  H01L2224/05001 ,  H01L2224/05023 ,  H01L2224/05026 ,  H01L2224/0508 ,  H01L2224/05184 ,  H01L2224/05568 ,  H01L2224/056 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/30105 ,  H01L2924/00014 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05166

摘要： A parasitic capacitance-preventing dummy solder bump structure on a substrate has at least one conductive layer formed on the substrate, a dielectric layer employed to cover the conductive layer, an under bump metallurgy layer (UBM layer) formed on the dielectric layer, and a solder bump formed on the UBM layer.

摘要翻译： 衬底上的寄生电容防止虚拟焊料凸块结构具有至少一个形成在衬底上的导电层，用于覆盖导电层的电介质层，形成在电介质层上的凸块下金属层（UBM层）和 焊料凸块形成在UBM层上。