公开(公告)号：US5576573A

公开(公告)日：1996-11-19

申请号：US454701

申请日：1995-05-31

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/112 ,  H01L29/423 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L27/112 ,  H01L29/42368 ,  Y10S438/981

Abstract: A multi-state memory cell for a mask ROM device. Source/drain regions are arranged on a substrate as strips extending along a first direction on the plane of the substrate and bit lines. Gate oxide layers are arranged on the substrate as strips extending along a second direction. Gate electrodes are each formed on top of each of the gate oxide layers as strips extending along the second direction. The gate oxide layers have a number of selected thickness' arranged in a differential series. Each of the transistor channel regions, together with their corresponding one of the neighboring source/drain pair, the gate oxide layer on top, and the gate electrodes further on top thereof constitute one of the memory cells that can have its threshold voltage varied among the differential series of thicknesses allowing for the storage of a multi-bit equivalent of memory content for the memory cell.

Abstract translation: 一种用于掩模ROM器件的多状态存储单元。 源极/漏极区域沿着衬底和位线的平面上沿着第一方向延伸的条带布置在衬底上。 栅极氧化物层沿着第二方向布置在基板上。 栅极电极分别形成在每个栅极氧化物层的顶部上，作为沿第二方向延伸的条带。 栅极氧化物层具有多个选定的厚度，以差分系列排列。 每个晶体管沟道区以及它们相应的一个源极/漏极对，顶部的栅极氧化物层和进一步在其顶部的栅电极构成一个存储单元，其可以使其阈值电压在 差分系列的厚度允许存储用于存储器单元的多位等效的存储器内容。

公开(公告)号：US5691234A

公开(公告)日：1997-11-25

申请号：US511065

申请日：1995-08-03

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/02 ,  H01L21/28

CPC classification number: H01L27/0255

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract translation: 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

公开(公告)号：US5597753A

公开(公告)日：1997-01-28

申请号：US364318

申请日：1994-12-27

Applicant: Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

Inventor： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung ,  Yi-Chung Sheng

IPC: H01L21/8246

CPC classification number: H01L27/11246 ,  Y10S438/981

Abstract: An improved Read-Only-Memory (ROM) structure and a method of manufacturing said ROM device structure having an ultra-high-density of coded ROM cells, was achieved. The array of programmed ROM cells are composed of a single field effect transistor (FET) in each ROM cell. The improved ROM process utilizes the patterning of a ROM code insulating layer over each coded FET (cell) that is selected to remain in an off-state (nonconducting) when a gate voltage is applied. The remaining FETs (cells) have a thin gate oxide which switch to the on-state (conducting) when a gate voltage is applied. The thick ROM code insulating layer eliminates the need to code the FETs in the ROM memory cells by conventional high dose ion implantation. This eliminated the counter-doping of the buried bit lines by the implantation allowing for much tighter ground rules for the spacing between buried bit line. The elimination of the implant also reduces substantially the stand-by leakage current that is so important in battery operated electronic equipment, such as lap-top computers. The gate capacitance of the off-state cells is also substantially reduced because of the thick insulating layer, thereby reducing the RC time delay in the word lines and improving circuit performance.

Abstract translation: 实现了改进的只读存储器（ROM）结构和制造具有超高密度编码ROM单元的所述ROM器件结构的方法。 编程ROM单元的阵列由每个ROM单元中的单个场效应晶体管（FET）构成。 改进的ROM处理利用在施加栅极电压时选择为保持在截止状态（非导通）的每个编码的FET（单元）上的ROM代码绝缘层的图案化。 当施加栅极电压时，剩余的FET（单元）具有薄的栅极氧化物，其切换到导通状态（导通）。 粗ROM代码绝缘层消除了通过常规高剂量离子注入对ROM存储单元中的FET进行编码的需要。 这通过注入消除了掩埋位线的反掺杂，允许掩埋位线之间的间隔更紧密的基本规则。 植入物的消除也大大降低了备用泄漏电流，这在电池供电的电子设备如笔记本电脑中如此重要。 由于厚的绝缘层，断态单元的栅极电容也显着减小，从而减小了字线中的RC时间延迟并提高了电路性能。

公开(公告)号：US5382534A

公开(公告)日：1995-01-17

申请号：US254534

申请日：1994-06-06

Applicant: Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung

Inventor： Shing-Ren Sheu ,  Kuan-Cheng Su ,  Chen-Hui Chung

IPC: H01L21/336 ,  H01L29/08 ,  H01L29/10 ,  H01L21/265

CPC classification number: H01L29/66636 ,  H01L29/0847 ,  H01L29/1083

Abstract: The invention describes recessed buried conductive regions formed in a trench in the substrate that provides a smooth surface topology, smaller devices and improved device performance. The buried regions have two conductive regions, the first on the trench sidewalls, the second on the trench bottom. In addition, two buried layers are formed between adjacent buried conductive regions: a threshold voltage layer near the substrate surface and an anti-punchthrough layer formed at approximately the same depth as the conductive regions on the trench bottoms. The first conductive region and the anti-punchthrough layer have the effect of increasing the punchthru voltage without increasing the threshold voltage. The first and second regions also lowers the resistivity of the buried regions allowing use of smaller line pitches and therefore smaller devices. Overall, the recessed conductive regions and the two buried layers allow the formation of smaller devices with improved performance.

Abstract translation: 本发明描述了形成在衬底中的沟槽中的凹入的埋入导电区域，其提供了平滑的表面拓扑，较小的器件和改进的器件性能。 掩埋区域具有两个导电区域，第一个在沟槽侧壁上，第二个在沟槽底部。 此外，在相邻的掩埋导电区域之间形成两个掩埋层：在衬底表面附近的阈值电压层和形成在与沟槽底部上的导电区域大致相同深度的抗穿通层。 第一导电区域和抗穿通层具有增加穿透电压而不增加阈值电压的效果。 第一和第二区域也降低了掩埋区域的电阻率，从而允许使用较小的线间距并因此使用较小的器件。 总的来说，凹入的导电区域和两个掩埋层允许形成具有改进的性能的较小的器件。

公开(公告)号：US6093626A

公开(公告)日：2000-07-25

申请号：US897229

申请日：1997-07-29

Applicant: Kuan-Cheng Su ,  Shing-Ren Sheu

Inventor： Kuan-Cheng Su ,  Shing-Ren Sheu

IPC: H01L27/02 ,  H01L21/331 ,  H01L21/22 ,  H01L21/26

CPC classification number: H01L27/0255

Abstract: A method for eliminating plasma-induced charging damage during manufacture of an integrated circuit is described. A semiconductor substrate having a first conductivity type is provided. An oxide layer is formed on the semiconductor substrate. An opening is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit, but whereby the buried contact prevents the charging damage.

Abstract translation: 描述了在集成电路的制造期间消除等离子体引起的充电损坏的方法。 提供具有第一导电类型的半导体衬底。 在半导体基板上形成氧化物层。 在氧化物层中形成开口。 在氧化物层和开口中形成多晶硅层。 扩散区形成在半导体衬底中，通过开口与多晶硅层连接，具有与第一导电类型相反的第二导电类型，由此形成掩埋接触。 埋入触点通过基板连接到地面参考。 进行等离子体环境中的进一步处理，这通常会对集成电路造成充电损坏，但由此埋入触点防止充电损坏。

公开(公告)号：US08648421B2

公开(公告)日：2014-02-11

申请号：US13290399

申请日：2011-11-07

Applicant: Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

Inventor： Yung-Ju Wen ,  Chang-Tzu Wang ,  Tien-Hao Tang ,  Kuan-Cheng Su

IPC: H01L23/60

CPC classification number: H01L29/78 ,  H01L27/0266 ,  H01L29/41758 ,  H01L29/4966

Abstract: An electrostatic discharge (ESD) device is described, including a gate line, a source region at a first side of the gate line, a comb-shaped drain region disposed at a second side of the gate line and having comb-teeth parts, a salicide layer on the source region and the drain region, and contact plugs on the salicide layer on the source region and the drain region. Each comb-teeth part has thereon, at a tip portion thereof, at least one of the contact plugs.

Abstract translation: 描述了静电放电（ESD）器件，包括栅极线，栅极线第一侧的源极区域，设置在栅极线的第二侧并具有梳齿部分的梳状漏极区域， 源极区域和漏极区域上的自对准硅化物层，以及源极区域和漏极区域上的自对准硅化物层上的接触塞。 每个梳齿部分在其顶端部分上具有至少一个接触塞。

公开(公告)号：US20120166130A1

公开(公告)日：2012-06-28

申请号：US12979914

申请日：2010-12-28

Applicant: Yun-Chi YANG ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

Inventor： Yun-Chi YANG ,  Yen-Song Liu ,  Chin-Hsien Chen ,  Sheng-Yu Wu ,  Kuan-Cheng Su

IPC: G06F19/00

CPC classification number: G11C29/52 ,  G01R31/287 ,  G11C29/42 ,  G11C29/44 ,  G11C29/56008 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: A method for evaluating failure rate, which is applied to a plurality of semiconductor chips with error checking and correcting function includes the following steps. A first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of first failure bit counting values. The error checking and correcting function of each of the semiconductor chips is off. An aging test is applied to the semiconductor chips. A second read-write test operation as the first read-write test operation is applied to the semiconductor chips, thereby obtaining a plurality of second failure bit counting values. The number of the semiconductor chips, the first failure bit counting values, the second failure bit counting values and an error checking and correcting coefficient are calculated to obtain a failure rate of the semiconductor chips.

Abstract translation: 一种用于评估故障率的方法，其应用于具有错误检查和校正功能的多个半导体芯片包括以下步骤。 对半导体芯片应用第一读写测试操作，从而获得多个第一故障比特计数值。 每个半导体芯片的错误检查和校正功能关闭。 对半导体芯片进行老化试验。 作为第一读写测试操作的第二读写测试操作被应用于半导体芯片，从而获得多个第二故障位计数值。 计算半导体芯片的数量，第一故障比特计数值，第二故障比特计数值和错误校验系数，以获得半导体芯片的故障率。

公开(公告)号：US07589551B1

公开(公告)日：2009-09-15

申请号：US12107772

申请日：2008-04-23

Applicant: Yun-Chi Yang ,  Chao-Yung Lai ,  Chao-Yang Lin ,  Cheng-Li Lin ,  Kuan-Cheng Su

Inventor： Yun-Chi Yang ,  Chao-Yung Lai ,  Chao-Yang Lin ,  Cheng-Li Lin ,  Kuan-Cheng Su

IPC: G01R31/26 ,  G01R31/02

CPC classification number: G01R31/2858 ,  G01R31/2884

Abstract: To make an alternating current (AC) stress test easier to perform in a wafer, an AC stress test circuit for performing the AC stress test on a test device fabricated in a test region of the wafer includes an oscillator module fabricated in the test region, a diode module fabricated in the test region coupled to an output of the oscillator module, and a select transistor fabricated in the test region having a gate terminal coupled to an output of the diode module, a second terminal coupled to a gate of the test device, and a third terminal coupled to a test voltage source.

Abstract translation: 为了在晶片中更容易进行交流（AC）应力测试，用于对在晶片的测试区域中制造的测试装置进行AC应力测试的AC应力测试电路包括在测试区域中制造的振荡器模块， 制造在耦合到振荡器模块的输出的测试区域中的二极管模块，以及制造在测试区域中的选择晶体管，其具有耦合到二极管模块的输出的栅极端子，耦合到测试装置的栅极的第二端子 以及耦合到测试电压源的第三端子。

公开(公告)号：US06171899B2

公开(公告)日：2001-01-09

申请号：US09267535

申请日：1999-03-12

Applicant: Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

Inventor： Fu-Tai Liou ,  Water Lur ,  Kuan-Cheng Su ,  Juan-Yuan Wu

IPC: H01L218242

CPC classification number: H01L28/60 ,  H01L21/76838

Abstract: A method for fabricating a capacitor. A first metal layer is formed on a provided substrate. A dielectric film is formed on the first metal layer. The dielectric film can be a mono-layer structure or a multi-layer structure comprising various dielectric materials. A rapid thermal process (RTP), such as a rapid thermal annealing, or a plasma treatment is performed to enhance the quality of the dielectric film. A photolithography and etching process is performed to remove a part of the dielectric film and the first metal layer to expose a part of the inter-layer dielectric layer. The remaining first conductive layer is used as a lower electrode. A conventional interconnect process is performed on the exposed inter-layer dielectric layer and on the dielectric film. For example, a glue layer is formed on the exposed inter-layer dielectric layer and on the dielectric film. A second metal layer is formed on the glue layer. A photolithography and etching process is performed to remove a part of the second conductive layer. The second metal layer remaining on the inter-layer dielectric layer is used as a wiring line for interconnection. The glue layer remaining on the dielectric film is used as an upper electrode.

Abstract translation: 一种制造电容器的方法。 在所提供的基板上形成第一金属层。 在第一金属层上形成电介质膜。 电介质膜可以是单层结构或包括各种介电材料的多层结构。 进行快速热处理（RTP），例如快速热退火或等离子体处理，以提高电介质膜的质量。 进行光刻和蚀刻处理以去除电介质膜和第一金属层的一部分以暴露层间电介质层的一部分。 剩余的第一导电层用作下电极。 在暴露的层间电介质层和电介质膜上进行常规的互连工艺。 例如，在暴露的层间电介质层和电介质膜上形成胶层。 第二金属层形成在胶层上。 执行光刻和蚀刻工艺以去除第二导电层的一部分。 残留在层间电介质层上的第二金属层用作互连布线。 残留在电介质膜上的胶层用作上电极。

公开(公告)号：US5665995A

公开(公告)日：1997-09-09

申请号：US429603

申请日：1995-04-27

Applicant: Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

Inventor： Chen-Chiu Hsue ,  Shing-Ren Shev ,  Kuan-Cheng Su ,  Chen-Hui Chung

IPC: H01L21/8246 ,  H01L27/112 ,  H01L29/76

CPC classification number: H01L27/1126 ,  H01L27/112

Abstract: A ROM device with an array of cells has conductors formed in a substrate. Insulation is formed, and parallel conductors are formed orthogonally to the line regions, as thin as about 2000 .ANG.. Glass insulation having a thickness of about 3000 .ANG. or less, formed over the conductors is is reflowed. Contacts and a metal layer on the glass insulation are formed. Resist is patterned and used for etching the resist pattern in the metal. Removal of the second resist and device passivation with a layer having a thickness of about 1000 .ANG., precede activation of the impurity ions by annealing the device at less than or equal to about 520.degree. C. in a reducing gas atmosphere. After resist removal, a second resist is formed and exposed with a custom code pattern to form a mask. Ions are implanted into the substrate with a dosage of between about 1 E 14 and 3 E 14 atoms/cm.sup.2 with an energy of less than or equal to 200 keV adjacent to the conductors through the openings in the insulation.

Abstract translation: 具有单元阵列的ROM器件具有形成在衬底中的导体。 形成绝缘体，平行导体与线区域正交形成，薄至约2000安。 在导体上形成厚度约为3000或更小的玻璃绝缘体被回流。 形成玻璃绝缘体上的触点和金属层。 抗蚀剂被图案化并用于蚀刻金属中的抗蚀剂图案。 在还原气体气氛中，通过在小于或等于约520℃退火器件使杂质离子激活之前，用厚度约为1000的层去除第二抗蚀剂和器件钝化。 抗蚀剂除去后，形成第二抗蚀剂并用定制的编码图案曝光以形成掩模。 离子以约1E14和3E14原子/ cm2的剂量注入到基底中，其能量小于或等于200keV，通过绝缘体中的开口与导体相邻。