公开(公告)号：US07117460B2

公开(公告)日：2006-10-03

申请号：US10794003

申请日：2004-03-04

申请人： Shou-Zen Chang ,  Wei-Ming Chen ,  Hsien-Pin Hu ,  Chia-Nan Lee

发明人： Shou-Zen Chang ,  Wei-Ming Chen ,  Hsien-Pin Hu ,  Chia-Nan Lee

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5036

摘要： A method is disclosed for modifying a device dimension extraction model. After collecting in-line data with regard to at least one feature of a device for one or more layouts, a proximity and linearity effect with regard to the feature based on the collected data is determined. Further, the device's electrically active region (OD) drawn size effect with regard to the feature is also determined based on the collected data. The dimension extraction model is modified based on at least two of the above three characterized effects.

摘要翻译： 公开了一种用于修改设备尺寸提取模型的方法。 在收集关于一个或多个布局的设备的至少一个特征的在线数据之后，确定关于基于所收集的数据的特征的接近度和线性效应。 此外，还根据所收集的数据确定装置的关于特征的电活动区域（OD）拉伸尺寸效应。 基于上述三个特征效果中的至少两个来修改尺寸提取模型。

公开(公告)号：US20050198603A1

公开(公告)日：2005-09-08

申请号：US10794003

申请日：2004-03-04

申请人： Shou-Zen Chang ,  Wei-Ming Chen ,  Hsien-Pin Hu ,  Chia-Nan Lee

发明人： Shou-Zen Chang ,  Wei-Ming Chen ,  Hsien-Pin Hu ,  Chia-Nan Lee

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A method is disclosed for modifying a device dimension extraction model. After collecting in-line data with regard to at least one feature of a device for one or more layouts, a proximity and linearity effect with regard to the feature based on the collected data is determined. Further, the device's electrically active region (OD) drawn size effect with regard to the feature is also determined based on the collected data. The dimension extraction model is modified based on at least two of the above three characterized effects.

摘要翻译： 公开了一种用于修改设备尺寸提取模型的方法。 在收集关于一个或多个布局的设备的至少一个特征的在线数据之后，确定关于基于所收集的数据的特征的接近度和线性效应。 此外，还根据所收集的数据确定装置的关于特征的电活动区域（OD）拉伸尺寸效应。 基于上述三个特征效果中的至少两个来修改尺寸提取模型。

公开(公告)号：US06303448B1

公开(公告)日：2001-10-16

申请号：US09187303

申请日：1998-11-05

申请人： Shou-Zen Chang ,  Chao-Chieh Tsai

发明人： Shou-Zen Chang ,  Chao-Chieh Tsai

IPC分类号： H01L21336

CPC分类号： H01L29/66621 ,  H01L29/665 ,  H01L29/7834

摘要： The present invention provides a method for fabricating elevated and drain structures on a substrate. A first insulating layer is formed over a silicon substrate. A first barrier layer is formed over the first insulating layer. The first barrier layer, the first insulating layer and the substrate are patterned to form a trench. Ions are implanted into the substrate in the trench. A gate oxide layer is formed on the substrate in the trench. A polysilicon layer is deposited over the gate oxide layer and the barrier layer. The polysilicon layer is planarized using a chemical mechanical polishing process (CMP) stopping on the barrier layer to form a novel recessed gate. The barrier layer and the first insulating layer are removed. Lightly doped source/drain regions (LDD) are formed adjacent to the recessed gate. Spacers are formed on the sidewalls of the recessed gate. Source and drain regions are formed adjacent to the spacers. Salicide layers are formed on the source and drain regions and on the top of the recessed gate.

摘要翻译： 本发明提供了一种在衬底上制造升高和漏极结构的方法。 在硅衬底上形成第一绝缘层。 在第一绝缘层上形成第一阻挡层。 图案化第一阻挡层，第一绝缘层和衬底以形成沟槽。 离子被植入到沟槽中的衬底中。 栅极氧化层形成在沟槽中的衬底上。 在栅极氧化物层和阻挡层上沉积多晶硅层。 使用在阻挡层上停止的化学机械抛光工艺（CMP）来平坦化多晶硅层以形成新颖的凹入栅极。 去除阻挡层和第一绝缘层。 在凹入栅极附近形成轻掺杂的源/漏区（LDD）。 间隔件形成在凹槽的侧壁上。 源极和漏极区域邻近间隔物形成。 在源极和漏极区域以及凹陷栅极的顶部上形成自对准硅层。

公开(公告)号：US09105744B2

公开(公告)日：2015-08-11

申请号：US13410207

申请日：2012-03-01

申请人： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

发明人： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L21/84

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0629 ,  H01L29/0642 ,  H01L29/66636 ,  H01L29/6681

摘要： Semiconductor devices and manufacturing and design methods thereof are disclosed. In one embodiment, a semiconductor device includes an active FinFET disposed over a workpiece comprising a first semiconductive material, the active FinFET comprising a first fin. An electrically inactive FinFET structure is disposed over the workpiece proximate the active FinFET, the electrically inactive FinFET comprising a second fin. A second semiconductive material is disposed between the first fin and the second fin.

摘要翻译： 公开了半导体器件及其制造和设计方法。 在一个实施例中，半导体器件包括设置在包括第一半导体材料的工件上的有源FinFET，所述有源FinFET包括第一鳍片。 非活性FinFET结构设置在靠近有源FinFET的工件上方，该非活性FinFET包括第二鳍片。 第二半导体材料设置在第一鳍片和第二鳍片之间。

公开(公告)号：US09054188B2

公开(公告)日：2015-06-09

申请号：US13404819

申请日：2012-02-24

申请人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

发明人： I-Ming Chang ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang ,  Clement Hsingjen Wann ,  Tung Ying Lee ,  Cheng-Long Chen ,  Jui-Chien Huang

IPC分类号： H01L21/3205 ,  H01L21/683 ,  H01L21/687 ,  H01L21/31 ,  H01L29/78 ,  H01L29/10 ,  H01L29/66

CPC分类号： H01L21/687 ,  H01L21/6838 ,  H01L29/1054 ,  H01L29/66545 ,  H01L29/7845 ,  H01L29/7847 ,  H01L29/7848 ,  H01L29/785

摘要： An apparatus for and a method of forming a semiconductor structure is provided. The apparatus includes a substrate holder that maintains a substrate such that the processing surface is curved, such as a convex or a concave shape. The substrate is held in place using point contacts, a plurality of continuous contacts extending partially around the substrate, and/or a continuous ring extending completely around the substrate. The processing may include, for example, forming source/drain regions, channel regions, silicides, stress memorization layers, or the like.

摘要翻译： 提供了一种形成半导体结构的装置和方法。 该装置包括：基板保持件，其保持基板，使得处理表面是弯曲的，例如凸形或凹形。 基板使用点接触保持就位，多个连续接触部分围绕基板延伸，和/或完全围绕基板延伸的连续环。 处理可以包括例如形成源极/漏极区域，沟道区域，硅化物，应力存储层等。

公开(公告)号：US08551841B2

公开(公告)日：2013-10-08

申请号：US13345473

申请日：2012-01-06

申请人： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

发明人： Tung Ying Lee ,  Wen-Huei Guo ,  Chih-Hao Chang ,  Shou-Zen Chang

IPC分类号： H01L21/336

CPC分类号： H01L27/088 ,  H01L27/0255 ,  H01L29/66795 ,  H01L29/785

摘要： A method includes forming an ESD diode including performing an epitaxy growth to form an epitaxy region comprising silicon and substantially free from germanium. The epitaxy region is doped with a p-type impurity to form a p-type region, wherein the p-type region forms an anode of the ESD diode.

摘要翻译： 一种方法包括形成ESD二极管，包括进行外延生长以形成包含硅且基本上不含锗的外延区。 外延区域掺杂有p型杂质以形成p型区域，其中p型区域形成ESD二极管的阳极。

公开(公告)号：US08313993B2

公开(公告)日：2012-11-20

申请号：US12358188

申请日：2009-01-22

申请人： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

发明人： Hag-Ju Cho ,  Anabela Veloso ,  HongYu Yu ,  Stefan Kubicek ,  Shou-Zen Chang

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823462 ,  H01L27/088 ,  H01L27/092 ,  H01L29/513

摘要： A dual work function semiconductor device and method for fabricating the same are disclosed. In one aspect, a device includes a first and second transistor on a first and second substrate region. The first and second transistors include a first gate stack having a first work function and a second gate stack having a second work function respectively. The first and second gate stack each include a host dielectric, a gate electrode comprising a metal layer, and a second dielectric capping layer therebetween. The second gate stack further has a first dielectric capping layer between the host dielectric and metal layer. The metal layer is selected to determine the first work function. The first dielectric capping layer is selected to determine the second work function.

摘要翻译： 公开了一种双功能半导体器件及其制造方法。 一方面，一种器件包括在第一和第二衬底区域上的第一和第二晶体管。 第一和第二晶体管包括分别具有第一功函数的第一栅极堆叠和具有第二功函数的第二栅极堆叠。 第一和第二栅极堆叠各自包括主电介质，包括金属层的栅电极和它们之间的第二电介质覆盖层。 第二栅极堆叠还在主介质和金属层之间具有第一介电覆盖层。 选择金属层以确定第一功函数。 选择第一介电覆盖层以确定第二功函数。

公开(公告)号：US6037204A

公开(公告)日：2000-03-14

申请号：US131321

申请日：1998-08-07

申请人： Shou-Zen Chang ,  Chaochieh Tsai ,  Chin-Hsiung Ho ,  Cheng Kun Lin

发明人： Shou-Zen Chang ,  Chaochieh Tsai ,  Chin-Hsiung Ho ,  Cheng Kun Lin

IPC分类号： H01L21/223 ,  H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8238

CPC分类号： H01L21/2236 ,  H01L21/26506 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823835 ,  H01L29/665

摘要： A method for forming salicide contacts and polycide conductive lines in integrated circuits is described which employs the ion implantation of both silicon and arsenic into polysilicon structures and into source/drain MOSFET elements is described. The method is effective in reducing gate-to-source/drain bridging in the manufacture of sub-micron CMOS integrated circuits and improving the conductivity of sub-micron wide polycide lines. Silicon is implanted into the polysilicon and into the source/drain surfaces forming a amorphized surface layer. Next a low dose, low energy arsenic implant is administered into the amorphized layer. The low dose shallow arsenic implant in concert with the amorphized layer initiates an equalized formation of titanium silicide over both NMOS and PMOS devices in CMOS integrated circuits without degradation of the PMOS devices. Amorphization by the electrically neutral silicon ions permits the use of a lower dose of arsenic than would be required if arsenic alone were implanted. In addition to amorphization, the implanted silicon prevents the formation of microvoids by providing silicon towards titanium silicide formation. The combined amorphization effect of the silicon and arsenic implants also facilitates a silicide phase transition on sub-micron wide polycide lines thereby improving their conductivity.

摘要翻译： 描述了在集成电路中形成硅化物接触和多硅化物导线的方法，其采用硅和砷的离子注入到多晶硅结构中并描述为源极/漏极MOSFET元件。 该方法在减少亚微米CMOS集成电路的制造中的栅极到源极/漏极桥接以及提高亚微米宽的多晶硅化物线的电导率方面是有效的。 将硅注入多晶硅并进入形成非晶化表面层的源极/漏极表面。 接下来，将低剂量的低能量砷植入物施用于非晶化层。 与非晶化层一致的低剂量浅砷植入物在CMOS集成电路中的NMOS和PMOS器件上均衡形成钛硅化物，而不会降低PMOS器件。 通过电中性硅离子的非晶化允许使用比单独砷植入所需的更低剂量的砷。 除了非晶化之外，注入的硅通过向硅化钛形成提供硅来防止形成微孔。 硅和砷植入物的组合非晶化效应也有助于亚微米宽多硅化物线上的硅化物相变，从而改善其导电性。