公开(公告)号：US09062389B2

公开(公告)日：2015-06-23

申请号：US13618564

申请日：2012-09-14

Applicant: Shu-Jen Han ,  Lian Guo ,  Xuesong Li

Inventor： Shu-Jen Han ,  Lian Guo ,  Xuesong Li

IPC: C25F7/00 ,  C25F5/00 ,  B32B38/10 ,  C25F3/02 ,  C01B31/04

CPC classification number: C25F7/00 ,  B32B38/10 ,  C01B32/186 ,  C25F3/02 ,  C25F5/00

Abstract: An electroplating etching apparatus includes a power supply to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.

Abstract translation: 电镀蚀刻装置包括用于输出电流的电源和构造成容纳电解质的容器。 阴极耦合到容器并且构造成与电解液流体连通。 阳极电连接到输出端，并且包括石墨烯层。 在石墨烯层上形成金属基底层，并响应于流过阳极的电流从石墨烯层中蚀刻出金属基底层。

公开(公告)号：US08785262B2

公开(公告)日：2014-07-22

申请号：US13610991

申请日：2012-09-12

Applicant: Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

Inventor： Damon B. Farmer ,  Aaron D. Franklin ,  Shu-Jen Han ,  George S. Tulevski

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/78669 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/0673 ,  H01L29/775 ,  H01L29/78678 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0516 ,  Y10S977/742

Abstract: Self-aligned carbon nanostructure field effect transistor structures are provided, which are foamed using selective dielectric deposition techniques. For example, a transistor device includes an insulating substrate and a gate electrode embedded in the insulating substrate. A dielectric deposition-prohibiting layer is formed on a surface of the insulating substrate surrounding the gate electrode. A gate dielectric is selectively formed on the gate electrode. A channel structure (such as a carbon nanostructure) is disposed on the gate dielectric A passivation layer is selectively formed on the gate dielectric. Source and drain contacts are formed on opposing sides of the passivation layer in contact with the channel structure. The dielectric deposition-prohibiting layer prevents deposition of dielectric material on a surface of the insulating layer surrounding the gate electrode when selectively forming the gate dielectric and passivation layer.

Abstract translation: 提供了自对准碳纳米结构场效应晶体管结构，其使用选择性电介质沉积技术发泡。 例如，晶体管器件包括绝缘衬底和嵌入绝缘衬底中的栅电极。 在围绕栅电极的绝缘基板的表面上形成介电沉积禁止层。 选择性地在栅电极上形成栅极电介质。 沟道结构（例如碳纳米结构）设置在栅极电介质上钝化层选择性地形成在栅极电介质上。 源极和漏极触点形成在与沟道结构接触的钝化层的相对侧上。 当选择性地形成栅极电介质和钝化层时，介电沉积禁止层防止介电材料沉积在围绕栅电极的绝缘层的表面上。

公开(公告)号：US08680646B2

公开(公告)日：2014-03-25

申请号：US13605529

申请日：2012-09-06

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L29/00

CPC classification number: H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

Abstract: A device and method for device fabrication include forming a buried gate electrode in a dielectric substrate and patterning a stack having a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

Abstract translation: 用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅极电极，并且在掩埋栅电极上图案化具有高介电常数层，碳基半导电层和保护层的叠层。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

公开(公告)号：US20140076721A1

公开(公告)日：2014-03-20

申请号：US13617727

申请日：2012-09-14

Applicant: Shu-Jen Han ,  Lian Guo ,  Xuesong Li

Inventor： Shu-Jen Han ,  Lian Guo ,  Xuesong Li

IPC: C25F7/00

CPC classification number: C25F7/00 ,  B32B38/10 ,  C01B32/186 ,  C25F3/02 ,  C25F5/00

Abstract: An electroplating etching apparatus includes a power to output current, and a container configured to contain an electrolyte. A cathode is coupled to the container and configured to fluidly communicate with the electrolyte. An anode is electrically connected to the output, and includes a graphene layer. A metal substrate layer is formed on the graphene layer, and is etched from the graphene layer in response to the current flowing through the anode.

Abstract translation: 电镀蚀刻装置包括输出电流的电力，以及容纳电解质的容器。 阴极耦合到容器并且构造成与电解液流体连通。 阳极电连接到输出端，并且包括石墨烯层。 在石墨烯层上形成金属基底层，并响应于流过阳极的电流从石墨烯层中蚀刻出金属基底层。

公开(公告)号：US20140042385A1

公开(公告)日：2014-02-13

申请号：US13587508

申请日：2012-08-16

Applicant: Aaron D. Franklin ,  Shu-jen Han ,  Joshua T. Smith ,  Paul M. Solomon

Inventor： Aaron D. Franklin ,  Shu-jen Han ,  Joshua T. Smith ,  Paul M. Solomon

IPC: H01L29/08 ,  B82Y99/00

CPC classification number: B82Y40/00 ,  B82Y10/00 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/775 ,  H01L51/0048 ,  H01L51/055 ,  H01L51/0558

Abstract: A method of fabricating a semiconducting device is disclosed. A carbon nanotube is deposited on a substrate of the semiconducting device. A first contact on the substrate over the carbon nanotube. A second contact on the substrate over the carbon nanotube, wherein the second contact is separated from the first contact by a gap. A portion of the substrate in the gap between the first contact and the second contact is removed.

Abstract translation: 公开了制造半导体器件的方法。 碳纳米管沉积在半导体器件的衬底上。 在碳纳米管上的衬底上的第一接触。 在碳纳米管上的衬底上的第二接触，其中第二接触件通过间隙与第一接触件分离。 第一触点和第二触点之间的间隙中的基板的一部分被去除。

公开(公告)号：US08610172B2

公开(公告)日：2013-12-17

申请号：US13326825

申请日：2011-12-15

Applicant: Dechao Guo ,  Shu-Jen Han ,  Edward William Kiewra ,  Kuen-Ting Shiu

Inventor： Dechao Guo ,  Shu-Jen Han ,  Edward William Kiewra ,  Kuen-Ting Shiu

IPC: H01L29/66

CPC classification number: H01L21/8258 ,  H01L21/823807 ,  H01L27/0605

Abstract: Techniques for employing different channel materials within the same CMOS circuit are provided. In one aspect, a method of fabricating a CMOS circuit includes the following steps. A wafer is provided having a first semiconductor layer on an insulator. STI is used to divide the first semiconductor layer into a first active region and a second active region. The first semiconductor layer is recessed in the first active region. A second semiconductor layer is epitaxially grown on the first semiconductor layer, wherein the second semiconductor layer comprises a material having at least one group III element and at least one group V element. An n-FET is formed in the first active region using the second semiconductor layer as a channel material for the n-FET. A p-FET is formed in the second active region using the first semiconductor layer as a channel material for the p-FET.

Abstract translation: 提供在同一CMOS电路内采用不同通道材料的技术。 一方面，制造CMOS电路的方法包括以下步骤。 提供了在绝缘体上具有第一半导体层的晶片。 STI用于将第一半导体层分成第一有源区和第二有源区。 第一半导体层凹入第一有源区。 第二半导体层在第一半导体层上外延生长，其中第二半导体层包括具有至少一个III族元素和至少一个V族元素的材料。 使用第二半导体层作为n-FET的沟道材料，在第一有源区中形成n-FET。 使用第一半导体层作为p-FET的沟道材料，在第二有源区中形成p-FET。

公开(公告)号：US08524614B2

公开(公告)日：2013-09-03

申请号：US12955203

申请日：2010-11-29

Applicant: Kuen-Ting Shiu ,  Dechao Guo ,  Shu-Jen Han ,  Edward W. Kiewra ,  Masaharu Kobayashi

Inventor： Kuen-Ting Shiu ,  Dechao Guo ,  Shu-Jen Han ,  Edward W. Kiewra ,  Masaharu Kobayashi

IPC: H01L21/31

CPC classification number: H01L29/0603 ,  H01L21/28158 ,  H01L21/28264 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/7833

Abstract: The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.

Abstract translation: 本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度 单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

公开(公告)号：US08513081B2

公开(公告)日：2013-08-20

申请号：US13272349

申请日：2011-10-13

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L21/336

CPC classification number: H01L21/2822 ,  H01L21/26506 ,  H01L21/823412 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545

Abstract: A method includes providing a wafer that has a semiconductor layer having an insulator layer disposed on the semiconductor layer. The insulator layer has openings made therein to expose a surface of the semiconductor layer, where each opening corresponds to a location of what will become a transistor channel in the semiconductor layer disposed beneath a gate stack. The method further includes depositing a high dielectric constant gate insulator layer so as to cover the exposed surface of the semiconductor layer and sidewalls of the insulator layer; depositing a gate metal layer that overlies the high dielectric constant gate insulator layer; and implanting Carbon through the gate metal layer and the underlying high dielectric constant gate insulator layer so as to form in an upper portion of the semiconductor layer a Carbon-implanted region having a concentration of Carbon selected to establish a voltage threshold of the transistor.

Abstract translation: 一种方法包括提供具有设置在半导体层上的绝缘体层的半导体层的晶片。 绝缘体层具有在其中形成的开口以暴露半导体层的表面，其中每个开口对应于在栅叠层下方的半导体层中将成为晶体管沟道的位置。 该方法还包括沉积高介电常数栅极绝缘体层以覆盖半导体层的暴露表面和绝缘体层的侧壁; 沉积覆盖在高介电常数栅极绝缘体层上的栅极金属层; 以及通过栅极金属层和下面的高介电常数栅极绝缘体层注入碳以便在半导体层的上部形成具有选定的碳浓度的碳注入区域，以建立晶体管的电压阈值。

公开(公告)号：US08455365B2

公开(公告)日：2013-06-04

申请号：US13111615

申请日：2011-05-19

Applicant: Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

Inventor： Dechao Guo ,  Shu-Jen Han ,  Keith Kwong Hon Wong ,  Jun Yuan

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L29/66515 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/41733 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/78684 ,  H01L51/0045 ,  H01L51/0048 ,  H01L51/0525 ,  H01L51/0545

Abstract: A device and method for device fabrication includes forming a buried gate electrode in a dielectric substrate and patterning a stack that includes a high dielectric constant layer, a carbon-based semi-conductive layer and a protection layer over the buried gate electrode. An isolation dielectric layer formed over the stack is opened to define recesses in regions adjacent to the stack. The recesses are etched to form cavities and remove a portion of the high dielectric constant layer to expose the carbon-based semi-conductive layer on opposite sides of the buried gate electrode. A conductive material is deposited in the cavities to form self-aligned source and drain regions.

Abstract translation: 一种用于器件制造的器件和方法包括在电介质衬底中形成掩埋栅电极，并且在掩埋栅电极之上构图包括高介电常数层，碳基半导电层和保护层的堆叠。 在叠层上形成的绝缘介电层被打开以在与堆叠相邻的区域中限定凹陷。 蚀刻凹槽以形成空腔并去除高介电常数层的一部分以暴露在掩埋栅电极的相对侧上的碳基半导体层。 导电材料沉积在空腔中以形成自对准的源区和漏区。

公开(公告)号：US20130130446A1

公开(公告)日：2013-05-23

申请号：US13605238

申请日：2012-09-06

Applicant: Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

Inventor： Qing Cao ,  Dechao Guo ,  Shu-Jen Han ,  Yu Lu ,  Keith Kwong Hon Wong

IPC: H01L21/336 ,  B82Y40/00

CPC classification number: H01L51/057 ,  B82Y10/00 ,  B82Y30/00 ,  H01L29/125 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/7827 ,  H01L51/0045 ,  H01L51/0048 ,  Y10S977/742 ,  Y10S977/842 ,  Y10S977/938

Abstract: A fin structure including a vertical alternating stack of a first isoelectric point material layer having a first isoelectric point and a second isoelectric material layer having a second isoelectric point less than the first isoelectric point is formed. The first and second isoelectric point material layers become oppositely charged in a solution with a pH between the first and second isoelectric points. Negative electrical charges are imparted onto carbon nanotubes by an anionic surfactant to the solution. The electrostatic attraction causes the carbon nanotubes to be selectively attached to the surfaces of the first isoelectric point material layer. Carbon nanotubes are attached to the first isoelectric point material layer in self-alignment along horizontal lengthwise directions of the fin structure. A transistor can be formed, which employs a plurality of vertically aligned horizontal carbon nanotubes as the channel.

Abstract translation: 形成包括具有第一等电点的第一等电点材料层和具有小于第一等电点的第二等电点的第二等电子材料层的垂直交替堆叠的鳍结构。 第一和第二等电点材料层在具有第一和第二等电点之间的pH的溶液中相反地充电。 通过阴离子表面活性剂将负电荷赋予碳纳米管。 静电引力使得碳纳米管选择性地附着在第一等电点材料层的表面上。 碳纳米管沿翅片结构的水平长度方向自对准地附接到第一等电点材料层。 可以形成晶体管，其采用多个垂直排列的水平碳纳米管作为沟道。