公开(公告)号：US5459743A

公开(公告)日：1995-10-17

申请号：US275306

申请日：1994-07-15

Applicant: Naoki Fukuda ,  Shuji Yoshimura ,  Satoshi Kakuma

Inventor： Naoki Fukuda ,  Shuji Yoshimura ,  Satoshi Kakuma

IPC: H04M11/00 ,  H04L12/28 ,  H04L12/70 ,  H04L12/56

CPC classification number: H04L49/309 ,  H04L49/3009 ,  H04L49/3081 ,  H04L49/555 ,  H04L2012/5627 ,  H04L49/30 ,  H04L49/503

Abstract: In an address decision system in an ATM exchange, a table memory stores data showing relationships between VPI/VCI values and addresses. A latch circuit latches a VPI/VCI value contained in a cell transferred via a cell highway. A comparator circuit compares the VPI/VCI values stored in the table memory with the VPI/VCI value latched by the latch and generates a comparator output signal showing, in a normal operation, one of the addresses at which the VPI/VCI value from the latch circuit coincides with one of the VPI/VCI values in the table memory. An address decision unit encodes the comparator output signal and generates an encoded signal based on the comparator output signal. A decoder unit decodes the encoded signal and generates a decoded signal. A check unit receives the comparator output signal and the encoded signal and generates an error signal when the comparator output signal and the encoded signal do not match each other.

Abstract translation: 在ATM交换机的地址决定系统中，表存储器存储表示VPI / VCI值与地址之间的关系的数据。 锁存电路锁存通过单元高速公路传送的单元中包含的VPI / VCI值。 比较器电路将存储在表存储器中的VPI / VCI值与由锁存器锁存的VPI / VCI值进行比较，并产生比较器输出信号，该信号表示在正常操作中VPI / VCI值来自 锁存电路与表存储器中的一个VPI / VCI值一致。 地址决定单元对比较器输出信号进行编码，并根据比较器输出信号产生编码信号。 解码器单元解码编码信号并产生解码信号。 检查单元接收比较器输出信号和编码信号，并且当比较器输出信号和编码信号彼此不匹配时产生误差信号。

公开(公告)号：US5448720A

公开(公告)日：1995-09-05

申请号：US940248

申请日：1992-09-04

Applicant: Shiro Uriu ,  Shuji Yoshimura ,  Yoshihiro Uchida

Inventor： Shiro Uriu ,  Shuji Yoshimura ,  Yoshihiro Uchida

IPC: G06F11/16 ,  G06F11/20 ,  H04B1/74 ,  H04J3/14 ,  H04M3/22 ,  H04Q3/545 ,  H04J1/16

CPC classification number: G06F11/2038 ,  G06F11/16 ,  G06F11/2028 ,  H04B1/74 ,  H04J3/14 ,  H04Q3/54558

Abstract: An information processing system includes a simplex system and a duplex system in which at least two data transmitting systems are provided each capable of being an act system or a standby system. Each data transmitting system has a data acquiring unit. The simplex system includes a controller for controlling a selector to switch between the systems. When in a standby condition, the data acquiring unit of the respective data transmitting system in the duplex system issues an access request signal to a switching signal generating unit provided in the controller of the simplex system to request that the output of the selector be switched from the act system to the standby system in the duplex system. Upon receipt of the access request signal from the data acquiring unit in the standby system, the switching signal generating unit switches the selector to the standby system. As a result, status data acquired by the data acquiring unit in the simplex section is output to the data acquiring section in the standby system. The duplex system uses the status data to make a diagnosis of the standby system for its normality.

Abstract translation: 信息处理系统包括单工系统和双工系统，其中提供至少两个能够作为动作系统或备用系统的数据传输系统。 每个数据发送系统具有数据获取单元。 单工系统包括用于控制选择器在系统之间切换的控制器。 当处于待机状态时，双工系统中的相应数据发送系统的数据获取单元向单工系统的控制器中提供的切换信号产生单元发出访问请求信号，以请求将选择器的输出从 该系统到双工系统中的备用系统。 在备用系统中从数据获取单元接收到访问请求信号时，切换信号生成单元将选择器切换到备用系统。 结果，将数据获取单元在单工部分中获取的状态数据输出到待机系统中的数据获取部分。 双工系统使用状态数据来对备用系统进行正常诊断。

公开(公告)号：US5394396A

公开(公告)日：1995-02-28

申请号：US261890

申请日：1994-06-17

Applicant: Shuji Yoshimura ,  Satoshi Kakuma ,  Naoki Aihara ,  Yasuhiro Aso ,  Masami Murayama

Inventor： Shuji Yoshimura ,  Satoshi Kakuma ,  Naoki Aihara ,  Yasuhiro Aso ,  Masami Murayama

IPC: H04M3/36 ,  H04L12/813 ,  H04J3/14

CPC classification number: H04L12/5602 ,  H04L49/3081 ,  H04L2012/5636 ,  H04L2012/5651 ,  H04L2012/5652

Abstract: A supervision control system for an ATM cell switching system counts the number of cells transmitted from a subscriber in a predetermined duration unit, attaches a sign to the cells when the counted value exceeds a predetermined value, and discards the cells to which the sign is attached when a buffer does not have enough capacity during a cell multiplexation.

Abstract translation: 用于ATM信元交换系统的监控控制系统以预定持续时间为单位对从用户发送的小区数进行计数，当计数值超过预定值时，向小区附加符号，并丢弃符号附加到的小区 当缓冲器在单元复用期间没有足够的容量时。

公开(公告)号：US5369649A

公开(公告)日：1994-11-29

申请号：US731332

申请日：1991-07-17

Applicant: Masami Murayama ,  Satoshi Kakuma ,  Shuji Yoshimura

Inventor： Masami Murayama ,  Satoshi Kakuma ,  Shuji Yoshimura

IPC: H04L1/00 ,  H04L12/951 ,  H04M7/00 ,  H04Q11/04 ,  G06F11/10

CPC classification number: H04Q11/0478 ,  H04L2012/563

Abstract: An error check of a signaling data divided into divided signaling data transferred asynchronously in a unit of cells is performed in a signaling data receiving and processing unit in a digital exchange. The exchange is connected with terminal equipment arranged in a narrow band ISDN environment in a broadband ISDN system. The error check is performed by calculating an error check code for every byte of the signaling data as it is received, accumulating the result until the cyclic redundancy code, encountered in the last byte of the signaling data, is accumulated and performing matching between the accumulated result and a constant value produced based on the CRC system. The checking is performed while the signaling data is stored in a data memory in the signaling data receiving and processing unit. The data memory provided in the signaling data receiving and processing unit has memory regions capable of storing the signaling data sent from the terminal which is allocated as needed by a central controller of the digital exchange.

Abstract translation: 在数字交换中的信令数据接收和处理单元中执行分组为以小区为单位异步传送的分离信令数据的信令数据的错误检查。 该交换机与宽带ISDN系统中布置在窄带ISDN环境中的终端设备连接。 通过计算接收到的信令数据的每个字节的错误校验码来进行错误检查，累加结果，直到在信令数据的最后一个字节中遇到的循环冗余码被累积并执行累积的 结果和基于CRC系统产生的恒定值。 当信令数据存储在信令数据接收和处理单元中的数据存储器中时，执行检查。 提供在信令数据接收和处理单元中的数据存储器具有能够存储从数字交换机的中央控制器根据需要分配的从终端发送的信令数据的存储区域。

公开(公告)号：US5313453A

公开(公告)日：1994-05-17

申请号：US854888

申请日：1992-03-20

Applicant: Yoshihiro Uchida ,  Satoshi Kakuma ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Shuji Yoshimura ,  Masami Murayama

Inventor： Yoshihiro Uchida ,  Satoshi Kakuma ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Shuji Yoshimura ,  Masami Murayama

IPC: H04L1/00 ,  H04L12/26 ,  H04L12/56 ,  H04Q11/04 ,  H04J3/14

CPC classification number: H04L12/5601 ,  H04L1/0083 ,  H04L12/2697 ,  H04L43/50 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/309 ,  H04Q11/0478 ,  H04J2203/0019 ,  H04L2012/5628 ,  H04L2012/5672 ,  H04L2012/5681

Abstract: A first form of an ATM channel testing apparatus tests an ATM channel by having a test cell detector in each switch to detect whether or not the switch appropriately switches a test cell generated by a test cell generating trunk. A second form of an ATM channel testing apparatus easily tests an ATM channel by having test cell generators provided for the respective input highways sequentially generating test cells including test cell identifying information and input highway identifying information, and having test cell checkers provided respectively for the output highways simply tally the test cells by the respective input highways. A third form of an ATM channel testing apparatus tests an ATM channel with less pieces of hardware by having turnaround parts in respective ordinary trunks sequentially turn around a test cell generated by a test cell generating trunk to be finally returned to the test cell generating trunk. A fourth form of an ATM channel testing apparatus tests an ATM channel by having a test cell checker provided for each of output highways to examine whether or not the test data carried in respective octets of the payloads in extracted test cells are of consecutive values.

Abstract translation: ATM信道测试装置的第一形式通过在每个交换机中具有测试小区检测器来检测ATM信道，以检测交换机是否适当地切换由测试小区产生的中继线产生的测试小区。 ATM信道测试装置的第二种形式通过为相应的输入高速公路提供测试单元发生器来容易地测试ATM信道，该测试单元发生器依次产生包括测试单元识别信息和输入公路识别信息的测试单元，并且具有分别为输出提供的测试单元检查器 高速公路通过相应的输入高速公路简单地测试单元格。 ATM信道测试装置的第三种形式通过在相应的普通中继线中具有周转部分来顺序地转换由测试小区生成中继线产生的测试小区，以最终返回到测试小区生成中继线，来测试具有较少硬件的ATM信道。 ATM信道测试装置的第四种形式通过为每个输出高速公路提供测试单元检查来检测ATM信道，以检查提取的测试小区中有效载荷的相应八位字节中承载的测试数据是否是连续值。

公开(公告)号：US5185743A

公开(公告)日：1993-02-09

申请号：US651797

申请日：1991-02-07

Applicant: Masami Murayama ,  Atsuhisa Takahashi ,  Satoshi Kakuma ,  Shuji Yoshimura

Inventor： Masami Murayama ,  Atsuhisa Takahashi ,  Satoshi Kakuma ,  Shuji Yoshimura

IPC: H04Q1/30 ,  H04L12/70

CPC classification number: H04L12/5601 ,  H04L2012/5629 ,  H04L2012/563 ,  H04L2012/5636

Abstract: An index value output circuit outputs an index value in response to a VCI added to the first signaling cell outputted from a terminal unit. A switching data output circuit outputs switching data for determining a path for signaling cells, based on the index value. Hence, by revising the index value according to a congestion state of an ATM switch, the above path is dynamically changed. The same index value is inserted in the second and subsequent signaling cells outputted from the terminal unit. Because switching data are based on the same index value, all signaling cells from the same terminal units are fed to the same signaling terminator.