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    Signaling data receiving and processing unit provided in a broadband integrated services digital network
    3.
    发明授权
    Signaling data receiving and processing unit provided in a broadband integrated services digital network 失效
    在宽带综合业务数字网络中提供的信令数据接收和处理单元

    公开(公告)号：US5369649A

    公开(公告)日：1994-11-29

    申请号：US731332

    申请日：1991-07-17

    申请人： Masami Murayama ,  Satoshi Kakuma ,  Shuji Yoshimura

    发明人： Masami Murayama ,  Satoshi Kakuma ,  Shuji Yoshimura

    IPC分类号： H04L1/00 ,  H04L12/951 ,  H04M7/00 ,  H04Q11/04 ,  G06F11/10

    CPC分类号： H04Q11/0478 ,  H04L2012/563

    摘要： An error check of a signaling data divided into divided signaling data transferred asynchronously in a unit of cells is performed in a signaling data receiving and processing unit in a digital exchange. The exchange is connected with terminal equipment arranged in a narrow band ISDN environment in a broadband ISDN system. The error check is performed by calculating an error check code for every byte of the signaling data as it is received, accumulating the result until the cyclic redundancy code, encountered in the last byte of the signaling data, is accumulated and performing matching between the accumulated result and a constant value produced based on the CRC system. The checking is performed while the signaling data is stored in a data memory in the signaling data receiving and processing unit. The data memory provided in the signaling data receiving and processing unit has memory regions capable of storing the signaling data sent from the terminal which is allocated as needed by a central controller of the digital exchange.

    摘要翻译： 在数字交换中的信令数据接收和处理单元中执行分组为以小区为单位异步传送的分离信令数据的信令数据的错误检查。 该交换机与宽带ISDN系统中布置在窄带ISDN环境中的终端设备连接。 通过计算接收到的信令数据的每个字节的错误校验码来进行错误检查，累加结果，直到在信令数据的最后一个字节中遇到的循环冗余码被累积并执行累积的 结果和基于CRC系统产生的恒定值。 当信令数据存储在信令数据接收和处理单元中的数据存储器中时，执行检查。 提供在信令数据接收和处理单元中的数据存储器具有能够存储从数字交换机的中央控制器根据需要分配的从终端发送的信令数据的存储区域。

    Apparatus for testing ATM channels
    4.
    发明授权
    Apparatus for testing ATM channels 失效
    ATM通道测试装置

    公开(公告)号：US5313453A

    公开(公告)日：1994-05-17

    申请号：US854888

    申请日：1992-03-20

    申请人： Yoshihiro Uchida ,  Satoshi Kakuma ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Shuji Yoshimura ,  Masami Murayama

    发明人： Yoshihiro Uchida ,  Satoshi Kakuma ,  Naoyuki Izawa ,  Yasuhiro Aso ,  Shuji Yoshimura ,  Masami Murayama

    IPC分类号： H04L1/00 ,  H04L12/26 ,  H04L12/56 ,  H04Q11/04 ,  H04J3/14

    CPC分类号： H04L12/5601 ,  H04L1/0083 ,  H04L12/2697 ,  H04L43/50 ,  H04L49/1553 ,  H04L49/255 ,  H04L49/309 ,  H04Q11/0478 ,  H04J2203/0019 ,  H04L2012/5628 ,  H04L2012/5672 ,  H04L2012/5681

    摘要： A first form of an ATM channel testing apparatus tests an ATM channel by having a test cell detector in each switch to detect whether or not the switch appropriately switches a test cell generated by a test cell generating trunk. A second form of an ATM channel testing apparatus easily tests an ATM channel by having test cell generators provided for the respective input highways sequentially generating test cells including test cell identifying information and input highway identifying information, and having test cell checkers provided respectively for the output highways simply tally the test cells by the respective input highways. A third form of an ATM channel testing apparatus tests an ATM channel with less pieces of hardware by having turnaround parts in respective ordinary trunks sequentially turn around a test cell generated by a test cell generating trunk to be finally returned to the test cell generating trunk. A fourth form of an ATM channel testing apparatus tests an ATM channel by having a test cell checker provided for each of output highways to examine whether or not the test data carried in respective octets of the payloads in extracted test cells are of consecutive values.

    摘要翻译： ATM信道测试装置的第一形式通过在每个交换机中具有测试小区检测器来检测ATM信道，以检测交换机是否适当地切换由测试小区产生的中继线产生的测试小区。 ATM信道测试装置的第二种形式通过为相应的输入高速公路提供测试单元发生器来容易地测试ATM信道，该测试单元发生器依次产生包括测试单元识别信息和输入公路识别信息的测试单元，并且具有分别为输出提供的测试单元检查器 高速公路通过相应的输入高速公路简单地测试单元格。 ATM信道测试装置的第三种形式通过在相应的普通中继线中具有周转部分来顺序地转换由测试小区生成中继线产生的测试小区，以最终返回到测试小区生成中继线，来测试具有较少硬件的ATM信道。 ATM信道测试装置的第四种形式通过为每个输出高速公路提供测试单元检查来检测ATM信道，以检查提取的测试小区中有效载荷的相应八位字节中承载的测试数据是否是连续值。

    Subscriber information processing method in a connectionless data service
    5.
    发明授权
    Subscriber information processing method in a connectionless data service 失效
    无连接数据业务中的用户信息处理方法

    公开(公告)号：US5561662A

    公开(公告)日：1996-10-01

    申请号：US210149

    申请日：1994-03-17

    申请人： Satoshi Kakuma ,  Kazuo Hajikano ,  Masami Murayama ,  Shuji Yoshimura ,  Shiro Uriu ,  Jin Abe

    发明人： Satoshi Kakuma ,  Kazuo Hajikano ,  Masami Murayama ,  Shuji Yoshimura ,  Shiro Uriu ,  Jin Abe

    IPC分类号： H04L12/46 ,  H04L12/70 ,  H04Q11/04 ,  H04L12/56 ,  H04L12/26

    CPC分类号： H04L49/105 ,  H04L49/3081 ,  H04Q11/0478 ,  H04L2012/5615 ,  H04L2012/5645

    摘要： A switch interface unit, a monitor unit, and a control system interface unit are connected as external units to a highway to which a subscriber information processing unit is also connected so that a monitoring process, that is, a special study process, can be simplified and a cost charged for the subscriber information processing unit can be prevented from increasing greatly. Furthermore, in an accounting process, accounting parameters are accumulated in an accounting information accumulating unit for variations on compressed source addresses, not on source addresses. As a result, the accounting information accumulating unit, etc. can be realized with normal circuit elements only.

    摘要翻译： 开关接口单元，监视单元和控制系统接口单元作为外部单元连接到用户信息处理单元也连接到的高速公路，从而可以简化监视处理，即特殊研究过程 并且可以防止为用户信息处理单元收取的费用大大增加。 此外，在计费处理中，计费参数累积在计费信息累积单元中，用于压缩源地址的变化，而不是源地址。 结果，会计信息存储单元等只能用普通电路元件实现。

    Virtual channel converter and VCC table access method
    7.
    发明授权
    Virtual channel converter and VCC table access method 失效
    虚拟通道转换器和VCC表访问方式

    公开(公告)号：US5691977A

    公开(公告)日：1997-11-25

    申请号：US580534

    申请日：1995-12-29

    申请人： Shuji Yoshimura ,  Satoshi Kakuma ,  Masami Murayama ,  Shiro Uriu ,  Tadashi Hoshino

    发明人： Shuji Yoshimura ,  Satoshi Kakuma ,  Masami Murayama ,  Shiro Uriu ,  Tadashi Hoshino

    IPC分类号： H04M3/00 ,  H04L12/28 ,  H04L12/70 ,  H04Q3/00 ,  H04Q11/04 ,  H04L12/56

    CPC分类号： H04Q11/0478 ,  H04L49/3081 ,  H04L2012/5614 ,  H04L2012/5619

    摘要： In a data access device for writing into or read from a data conversion table on the basis of a clock signal extracted from a cell being transferred over a line, a clock signal generator of the invention generates a second clock signal which differs from the first clock signal extracted from an incoming cell. A write/read control unit writes data into or reads data for maintenance from the data conversion table on the basis of either the first clock signal or the second clock signal when the line is normal. In the event of the occurrence of a failure in the line, on the other hand, the write/read control circuit permits the data conversion table to be written into or read from for maintenance on the basis of the second clock signal.

    摘要翻译： 本发明的时钟信号发生器根据从通过线路传输的单元提取的时钟信号写入数据转换表或从数据转换表读取数据存取装置，产生与第一时钟不同的第二时钟信号 从进入的小区提取的信号。 写入/读取控制单元在线路正常时，基于第一时钟信号或第二时钟信号，将数据写入数据转换表或从数据转换表读取数据进行维护。 另一方面，在线路中出现故障的情况下，写入/读取控制电路允许数据转换表基于第二时钟信号写入或读取以进行维护。

    Procedure for switching-over systems
    8.
    发明授权
    Procedure for switching-over systems 失效
    切换系统的过程

    公开(公告)号：US5488606A

    公开(公告)日：1996-01-30

    申请号：US216149

    申请日：1994-03-21

    申请人： Satoshi Kakuma ,  Shuji Yoshimura ,  Kazuo Hajikano ,  Masami Murayama ,  Yuzo Okuyama

    发明人： Satoshi Kakuma ,  Shuji Yoshimura ,  Kazuo Hajikano ,  Masami Murayama ,  Yuzo Okuyama

    IPC分类号： H04Q3/00 ,  H04L12/70 ,  H04L29/14 ,  H04L12/56

    CPC分类号： H04L49/153 ,  H04L49/552 ,  H04L69/40 ,  H04L2012/5627 ,  H04L49/1523 ,  H04L49/30

    摘要： An ATM (asynchronous transfer mode) exchange has a buffer for system #0 and a buffer for system #1 providing P-MEM's for storing data including an A bit and for a VCI/VPI currently in use is set to "1'. Upon detecting a switchover between the systems, every B bit is reset to "0". When the exchange while changing from a master to a slave receives a cell having a slave indication and while changing from a slave to a master it receives a cell having a master indication, respective systems rewrite B bits for VCI/VPI's of respective cells to "1". In the meantime, each of the P-MEM's calculates exclusive "OR" operations between the A bit and the B bit for every VCI/VPI, and further obtains a disjunction among all the exclusive "OR" operations thus obtained. Then, when both P-MEM's obtain "0" for their respective disjunctions, cells are read out from one of the buffers in the system changing from a slave to a master. This enables the ATM exchange having a switch duplexed by mutually asynchronous active and backup systems to switchover the systems without causing a cell to be duplicated or lost.

    摘要翻译： ATM（异步传输模式）交换机具有用于系统＃0的缓冲器和用于系统＃1的缓冲器，提供用于存储包括A位的数据的P-MEM，并且当前使用的VCI / VPI被设置为“1” 检测系统之间的切换，每个B位复位为“0”，当从主机切换到从机的交换机接收到具有从机指示的单元，并且在从从机更改为主机时，接收具有 主指示，相应的系统将各单元的VCI / VPI的B位重写为“1”，同时每个P-MEM针对每个VCI / VPI计算A位和B位之间的独占“或”运算， 并且在所得到的所有排他“OR”运算中进一步获得分离，然后，当两个P-MEM对于它们各自的分离获得“0”时，从系统中的缓冲器之一读出小区从从属设备 主机，这使得ATM交换机具有通过相互异步双工的交换机 主动和备份系统切换系统，而不会导致单元被重复或丢失。