公开(公告)号：US08060766B2

公开(公告)日：2011-11-15

申请号：US12399736

申请日：2009-03-06

申请人： Georgios K. Konstadinidis ,  Sudhakar Bobba

发明人： Georgios K. Konstadinidis ,  Sudhakar Bobba

IPC分类号： G06F1/00 ,  H03B19/00

CPC分类号： G06F1/305 ,  G06F1/08 ,  G06F1/3203

摘要： A voltage droop monitoring and correcting circuit for a microprocessor includes: a monitor circuit configured to monitor voltage droops of the microprocessor and perform a temporary clock-skipping technique to compensate for the voltage droops. A method for monitoring and correcting voltage droops of a microprocessor includes: monitoring voltage droops of the microprocessor; and performing a temporary clock-skipping technique to compensate for the voltage droops. A computer system includes memory; a processor operatively connected to the memory; and computer-readable instructions stored in the memory for causing the processor to: monitor voltage droops of the microprocessor; and perform a temporary clock-skipping technique to compensate for the voltage droops.

摘要翻译： 用于微处理器的电压下降监视和校正电路包括：监视器电路，被配置为监视微处理器的电压下降并执行暂时的跳时技术以补偿电压下降。 用于监视和校正微处理器的电压下降的方法包括：监视微处理器的电压下降; 并执行临时跳时技术以补偿电压下降。 计算机系统包括存储器; 可操作地连接到存储器的处理器; 以及存储在存储器中的计算机可读指令，用于使处理器：监视微处理器的电压下降; 并执行临时的时钟跳跃技术来补偿电压下降。

公开(公告)号：US07098501B2

公开(公告)日：2006-08-29

申请号：US10360267

申请日：2003-02-05

申请人： Weiran Kong ,  Bernard Ho ,  David Greenhill ,  Sudhakar Bobba

发明人： Weiran Kong ,  Bernard Ho ,  David Greenhill ,  Sudhakar Bobba

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L28/40 ,  H01L21/76838 ,  H01L23/5223 ,  H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A capacitor structure in a semiconductor device is provided. The capacitor structure includes a first power rail on a topmost level of the semiconductor device, and a second power rail on the topmost level of the semiconductor device. The capacitor structure also includes a dielectric layer disposed over at least a portion of one of the first power rail and the second power rail. The capacitor structure further includes a conductive layer disposed over and between the first power rail and the second power rail where the conductive layer is in electrical contact with the power rail not having the dielectric layer, and the conductive layer is disposed over the dielectric layer.

摘要翻译： 提供半导体器件中的电容器结构。 电容器结构包括在半导体器件的最上层的第一电源轨和半导体器件的最上层的第二电源轨。 电容器结构还包括设置在第一电力轨道和第二电力轨道之一的至少一部分上的电介质层。 电容器结构还包括设置在第一电力轨道和第二电力轨道之上和之间的导电层，其中导电层与不具有电介质层的电力轨道电接触，并且导电层设置在介电层上。

公开(公告)号：US06976235B2

公开(公告)日：2005-12-13

申请号：US10246089

申请日：2002-09-18

申请人： Sudhakar Bobba ,  Gin Yee ,  Pradeep Trivedi

发明人： Sudhakar Bobba ,  Gin Yee ,  Pradeep Trivedi

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5036 ,  G06F2217/78

摘要： A method and apparatus for assigning a set of region-based voltage drop budgets to an integrated circuit is provided. Further, a method for partitioning an integrated circuit into optimal voltage drop regions includes analyzing the integrated circuit for worst-case voltage drop data. The worst-case voltage drop data is used to partition the integrated circuit into a set of voltage drop regions, wherein each voltage drop region is assigned a region-based voltage drop budget. The region-based voltage drop budget assigned to a particular voltage drop region is based on a worst-case voltage drop experienced by that voltage drop region.

摘要翻译： 提供了一种用于将一组基于区域的电压降预算分配给集成电路的方法和装置。 此外，用于将集成电路划分成最佳压降区域的方法包括分析集成电路以获得最坏情况的电压降数据。 最坏情况的电压降数据用于将集成电路分成一组电压降区域，其中每个电压降区域被分配有基于区域的电压降预算。 分配给特定电压降区域的基于区域的电压降预算是基于该压降区域经历的最坏情况的电压降。

公开(公告)号：US06882196B2

公开(公告)日：2005-04-19

申请号：US10198453

申请日：2002-07-18

申请人： Gin Yee ,  Sudhakar Bobba ,  Claude Gauthier ,  Dean Liu ,  Lynn Ooi ,  Pradeep Trivedi

发明人： Gin Yee ,  Sudhakar Bobba ,  Claude Gauthier ,  Dean Liu ,  Lynn Ooi ,  Pradeep Trivedi

IPC分类号： H03K3/017 ,  H03K5/00 ,  H03K5/156

CPC分类号： H03K5/1565 ,  H03K2005/00045

摘要： A device that uses an input clock signal to generate an output clock signal with a desired frequency is provided. The device uses a voltage controlled delay element that outputs a reset signal to a flip-flop dependent on a bias signal and the input clock signal. When triggered, the flip-flop outputs a transition on the output clock signal, which, in turn, serves as an input to a duty cycle corrector that generates the bias signal dependent on the configuration of the duty cycle corrector. The duty cycle corrector may be configured to generate the bias signal so as to be able to operatively control the duty cycle of the output clock signal.

摘要翻译： 提供了使用输入时钟信号来产生具有期望频率的输出时钟信号的装置。 该器件使用电压控制延迟元件，其根据偏置信号和输入时钟信号将触发器输出复位信号。 当触发时，触发器输出输出时钟信号的转变，输出时钟信号又作为占空比校正器的输入，占空比校正器根据占空比校正器的配置产生偏置信号。 占空比校正器可以被配置为产生偏置信号，以便能够可操作地控制输出时钟信号的占空比。

公开(公告)号：US06658629B1

公开(公告)日：2003-12-02

申请号：US10142187

申请日：2002-05-09

申请人： Sudhakar Bobba ,  Pradeep Trivedi ,  Tyler Thorp

发明人： Sudhakar Bobba ,  Pradeep Trivedi ,  Tyler Thorp

IPC分类号： G06F1750

CPC分类号： G06F17/5063 ,  G06F17/5036

摘要： A technique for optimizing decoupling capacitance on an integrated circuit while meeting leakage power constraints of the integrated circuit is provided. The technique involves the formulation of a linear optimization problem using physical characteristics and constraints of the integrated circuit, where a linear solution to the linear optimization problem yields an optimal decoupling capacitance presence on the integrated circuit.

摘要翻译： 提供了一种在满足集成电路的漏电功率限制的情况下优化集成电路上的去耦电容的技术。 该技术涉及使用集成电路的物理特性和约束来制定线性优化问题，其中线性优化问题的线性解决方案在集成电路上产生最佳的去耦电容。

公开(公告)号：US06629306B2

公开(公告)日：2003-09-30

申请号：US09997918

申请日：2001-11-30

申请人： Sudhakar Bobba ,  Tyler Thorp

发明人： Sudhakar Bobba ,  Tyler Thorp

IPC分类号： G06F1750

CPC分类号： H05K9/0039

摘要： A method for preferentially shielding a signal to increase implicit decoupling capacitance is provided. The signal is preferentially shielded by using a probability of the signal being at a specific value to determine where to route the signal. Further, an integrated circuit that preferentially shields a signal to increase decoupling capacitance by 2using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer system for preferentially shielding a signal to increase decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal. Further, a computer readable medium having executable instructions for preferentially shielding a signal to increase implicit decoupling capacitance by using a probability of the signal being at a specific value to determine where to route the signal.

摘要翻译： 提供了一种优先屏蔽信号以增加隐式去耦电容的方法。 优先通过使用信号处于特定值的概率来确定信号来确定信号的路由。 此外，集成电路通过利用信号处于特定值的概率来确定信号路由位置优先屏蔽信号以增加去耦电容。 此外，一种用于通过使用信号处于特定值的概率来确定信号的路由来优先屏蔽信号以增加去耦电容的计算机系统。 此外，具有可执行指令的计算机可读介质，用于优先屏蔽信号以通过使用信号处于特定值的概率来确定在何处路由信号来增加隐式解耦电容。

公开(公告)号：US06552576B1

公开(公告)日：2003-04-22

申请号：US10096611

申请日：2002-03-12

申请人： Sudhakar Bobba ,  Pradeep Trivedi

发明人： Sudhakar Bobba ,  Pradeep Trivedi

IPC分类号： H03K19094

CPC分类号： H03K17/162 ,  H03K17/6874

摘要： A transmission gate immune to noise that selectively delivers/draws charge to/from a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided. Further, an NMOS pass gate immune to noise that delivers charge to a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided. Further, a PMOS pass gate immune to noise that draws charge from a noisy input node in order to ensure that an output node is not adversely affected by the noise on the input node is provided.

摘要翻译： 提供对噪声免疫的传输门，其选择性地向噪声输入节点传送/抽取电荷，以便确保输出节点不受输入节点上的噪声的不利影响。 此外，提供了免于噪声的NMOS通道门，其将电荷传送到噪声输入节点，以便确保输出节点不受输入节点上的噪声的不利影响。 此外，提供了免于噪声的PMOS通孔，其从噪声输入节点吸取电荷，以确保输出节点不受输入节点上的噪声的不利影响。

公开(公告)号：US06495926B1

公开(公告)日：2002-12-17

申请号：US09997471

申请日：2001-11-29

申请人： Sudhakar Bobba ,  Tyler Thorp ,  Dean Liu

发明人： Sudhakar Bobba ,  Tyler Thorp ,  Dean Liu

IPC分类号： H01L2348

CPC分类号： H01L24/17 ,  H01L23/50 ,  H01L23/5286 ,  H01L2224/13099 ,  H01L2924/00014 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2224/0401

摘要： A 60 degree bump placement layout for an integrated circuit power grid is provided. This layout improves integrated circuit performance and reliability and gives an integrated circuit designer added flexibility and uniformity in designing the integrated circuit. Further, a patterned bump array for a top metal layer of an integrated circuit having a plurality of 60 degree bump placement structures is provided.

摘要翻译： 提供集成电路电网的60度凸块布置布局。 这种布局提高了集成电路的性能和可靠性，并为集成电路设计人员增加了设计集成电路的灵活性和均匀性。 此外，提供了具有多个60度凸块放置结构的集成电路的顶部金属层的图案化凸块阵列。

公开(公告)号：US06473883B1

公开(公告)日：2002-10-29

申请号：US09997437

申请日：2001-11-29

申请人： Sudhakar Bobba ,  Tyler Thorp

发明人： Sudhakar Bobba ,  Tyler Thorp

IPC分类号： G06F1750

CPC分类号： G06F17/5068

摘要： A method for improving integrated circuit by using a patterned bump layout on a layer of the integrated circuit is provided. The method creates various bump structures by varying an angle between a line from a reference bump to a first bump and a line from the reference bump to a second bump. By varying the angle, a designer may generate a particular bump structure that meets the needs of a particular design. Further, a particular bump placement may be repeated across all or a portion of the metal layer in order to create a patterned bump layout.

摘要翻译： 提供了一种通过在集成电路的层上使用图案化凸块布局来改善集成电路的方法。 该方法通过改变从参考凸起到第一凸起的线和从参考凸起到第二凸起的线之间的角度来产生各种凸起结构。 通过改变角度，设计者可以产生满足特定设计需要的特定凸起结构。 此外，可以在金属层的全部或一部分上重复特定的凸起布置，以便产生图案化的凸块布局。

公开(公告)号：US20110291630A1

公开(公告)日：2011-12-01

申请号：US12787135

申请日：2010-05-25

申请人： Georgios Konstadinidis ,  Sudhakar Bobba ,  David Greenhill

发明人： Georgios Konstadinidis ,  Sudhakar Bobba ,  David Greenhill

IPC分类号： G05F1/10

CPC分类号： H02M3/157 ,  H02M2001/0025

摘要： Disclosed is a digital voltage regulator system and method for mitigating voltage droop in an integrated circuit. If an unacceptable voltage droop is detected, the digital voltage regulator may take action to allow the power supply voltage to recover. A digital voltage regulator in accordance with embodiments discussed herein detects voltage droop by comparing a power supply voltage measurement with a threshold voltage. The threshold voltage may be calibrated based on power supply voltage measurements taken while the integrated circuit is operating.

摘要翻译： 公开了用于减轻集成电路中的电压下降的数字电压调节器系统和方法。 如果检测到不可接受的电压下降，则数字电压调节器可采取动作以允许电源电压恢复。 根据本文讨论的实施例的数字电压调节器通过将电源电压测量与阈值电压进行比较来检测电压下降。 阈值电压可以基于集成电路运行时所采用的电源电压测量来校准。