公开(公告)号：US20180323198A1

公开(公告)日：2018-11-08

申请号：US16031990

申请日：2018-07-10

Applicant: TC Lab, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC: H01L27/102 ,  H01L27/08 ,  H01L29/423 ,  H01L29/74 ,  G11C11/39 ,  H01L27/105 ,  H01L27/11 ,  H01L27/108

CPC classification number: H01L27/1027 ,  G11C11/39 ,  H01L27/0817 ,  H01L27/1023 ,  H01L27/1052 ,  H01L27/10805 ,  H01L27/11 ,  H01L29/42308 ,  H01L29/74

Abstract: A vertical thyristor memory array including: a vertical thyristor memory cell, the vertical thyristor memory cell including: a p+ anode; an n-base located below the p+ anode; a p-base located below the n-base; a n+ cathode located below the p-base; an isolation trench located around the vertical thyristor memory cell; an assist gate located in the isolation trench adjacent the n-base wherein an entire vertical height of the assist gate is positioned within an entire vertical height of the n-base.

公开(公告)号：US20180323197A1

公开(公告)日：2018-11-08

申请号：US16015168

申请日：2018-06-21

Applicant: TC Lab, Inc.

Inventor： Harry Luan ,  Bruce L. Bateman ,  Valery Axelrad ,  Charlie Cheng

IPC: H01L27/102 ,  H01L29/66 ,  H01L29/45 ,  H01L29/10 ,  H01L21/324 ,  H01L29/06 ,  H01L21/762 ,  H01L29/16 ,  H01L49/02

Abstract: Operations with reduced current overall are performed on single thyristor memory cells forming a volatile memory cell cross-point array. An operation is performed on at least one memory cell in a first group of memory cells out of a plurality of groups of memory cells coupled to a line. A first voltage is applied across the first group of memory cells for the operation and a lower second voltage is applied across the other groups of memory cells. The first voltage is then applied across a second group of memory cells while the second voltage is applied across the other groups including the first group of memory cells. These steps may repeated until the operations covers all the groups.

公开(公告)号：US11444084B2

公开(公告)日：2022-09-13

申请号：US17218020

申请日：2021-03-30

Applicant: TC Lab, Inc.

Inventor： Harry Luan

IPC: H01L29/66 ,  H01L27/10 ,  H01L23/535 ,  H01L27/108 ,  H01L29/74 ,  H01L21/02

Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

公开(公告)号：US20220148637A1

公开(公告)日：2022-05-12

申请号：US17488148

申请日：2021-09-28

Applicant: TC Lab, Inc.

Inventor： Bruce L. Bateman

IPC: G11C11/39 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C7/12 ,  G11C5/06

Abstract: A memory architecture for 3-dimensional thyristor cell arrays is disclosed. Thyristor memory cells are connected in a 3-dimensional cross-point array to form a bit line cluster. The bit line clusters are connected in parallel to sense amplifier and write circuits through multiplexer/demultiplexer circuits. Control circuits select one of the bit line clusters during a read or write operation while the non-selected bit line clusters are not activated to avoid disturbs and power consumption in the non-selected bit line clusters. The bit line clusters, multiplexer/demultiplexer circuits, and sense amplifier and write circuits from a memory array tile (MAT).

公开(公告)号：US11282840B2

公开(公告)日：2022-03-22

申请号：US16730939

申请日：2019-12-30

Applicant: TC Lab, Inc.

Inventor： Harry Luan ,  Valery Axelrad

IPC: H01L27/102 ,  H01L21/8229 ,  H01L27/108 ,  H01L27/11512 ,  G11C15/04 ,  H01L29/66 ,  G11C11/39 ,  H01L27/08

Abstract: Isolation between vertical thyristor memory cells in an array is improved with isolation regions between the vertical thyristor memory cells. The isolation regions are formed by electrically isolating cores surrounded by insulating material, such as silicon dioxide, in trenches between the memory cells. The electrically isolating cores may be tubes of air or conducting rods. Methods of constructing the isolation regions in a processes for manufacturing vertical thyristor memory cell arrays are also disclosed.

公开(公告)号：US20210233912A1

公开(公告)日：2021-07-29

申请号：US17229695

申请日：2021-04-13

Applicant: TC Lab, Inc.

Inventor： Harry Luan

IPC: H01L27/108 ,  H01L21/02 ,  H01L29/74 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

公开(公告)号：US10978297B1

公开(公告)日：2021-04-13

申请号：US15989097

申请日：2018-05-24

Applicant: TC Lab, Inc.

Inventor： Harry Luan

IPC: H01L21/332 ,  H01L21/02 ,  H01L29/74 ,  G11C17/06 ,  G11C11/39

Abstract: A method of making stacked lateral semiconductor devices is disclosed. The method includes depositing a stack of alternating layers of different materials. Slots or holes are cut through the layers for subsequent formation of single crystal semiconductor fences or pillars. When each of the alternating layers of one material are removed space is provided for formation of single crystal semiconductor devices between the remaining layers. The devices are doped as the single crystal silicon is formed.

公开(公告)号：US10964699B2

公开(公告)日：2021-03-30

申请号：US16801105

申请日：2020-02-25

Applicant: TC Lab, Inc.

Inventor： Harry Luan

IPC: H01L27/108 ,  H01L29/74 ,  H01L29/66 ,  H01L23/535 ,  H01L21/02

Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells and associated peripheral circuitry. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Methods of fabricating the array are described.

公开(公告)号：US20200328214A1

公开(公告)日：2020-10-15

申请号：US16914181

申请日：2020-06-26

Applicant: TC Lab, Inc.

Inventor： Harry Luan

IPC: H01L27/108 ,  H01L21/02 ,  H01L29/74 ,  H01L29/165 ,  H01L29/10 ,  H01L29/66

Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of thyristor memory cells with silicon-germanium base regions. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. Methods of fabricating the array are described.

公开(公告)号：US10748903B2

公开(公告)日：2020-08-18

申请号：US15957865

申请日：2018-04-19

Applicant: TC Lab, Inc.

Inventor： Harry Luan

IPC: H01L27/102 ,  H01L23/528 ,  H01L29/74 ,  H01L21/311 ,  H01L21/02 ,  H01L27/108 ,  H01L29/66 ,  H01L21/822 ,  H01L21/3105 ,  H01L21/768 ,  H01L21/265 ,  H01L21/306 ,  H01L21/027 ,  H01L27/06

Abstract: A semiconductor structure for a DRAM is described having multiple layers of arrays of memory cells. Memory cells in a vertical string extending through the layers have an electrical connection to one terminal of the memory cells in that string. Word lines couple the strings together. Each layer of the array also includes bit line connections to memory cells on that layer. Select transistors enable the use of folded bit lines. The memory cells preferably are thyristors. Methods of fabricating the array are described.