公开(公告)号：US20150015575A1

公开(公告)日：2015-01-15

申请号：US13938192

申请日：2013-07-09

Applicant: John G. Gierach ,  Travis T. Schluessler

Inventor： John G. Gierach ,  Travis T. Schluessler

IPC: G06T17/20

CPC classification number: G06T17/20 ,  G06T15/40

Abstract: Various embodiments are generally directed to an apparatus, method and other techniques for separating a group of polygons from a viewpoint of a scene into a dependent subgroup of polygons or a non-dependent subgroup of polygon and spatially sorting the non-dependent subgroup of polygons and the dependent group of polygons separately to form a sorted group of polygons.

Abstract translation: 各种实施例通常涉及一种用于将一组多边形从场景的视点分离成多边形的依赖子组或多个非依赖子组的装置，方法和其他技术，并且对多边形的非依赖子组进行空间分类， 多边形的依赖组分别形成多边形的排序组。

公开(公告)号：US08898494B2

公开(公告)日：2014-11-25

申请号：US13398641

申请日：2012-02-16

Applicant: Travis T. Schluessler ,  Russell J. Fenger

Inventor： Travis T. Schluessler ,  Russell J. Fenger

IPC: G06F1/32 ,  G06F9/50

CPC classification number: G06F1/3206 ,  G06F1/206 ,  G06F1/3203 ,  G06F1/3253 ,  G06F1/3287 ,  G06F1/329 ,  G06F9/50 ,  G06F9/5094 ,  Y02D10/16 ,  Y02D10/171 ,  Y02D10/22 ,  Y02D10/24

Abstract: An apparatus, method and system is described herein for efficiently balancing performance and power between processing elements based on measured workloads. If a workload of a processing element indicates that it is a bottleneck, then its performance may be increased. However, if a platform or integrated circuit including the processing element is already operating at a power or thermal limit, the increase in performance is counterbalanced by a reduction or cap in another processing elements performance to maintain compliance with the power or thermal limit. As a result, bottlenecks are identified and alleviated by balancing power allocation, even when multiple processing elements are operating at a power or thermal limit.

Abstract translation: 这里描述了一种装置，方法和系统，用于基于测量的工作负载有效地平衡处理元件之间的性能和功率。 如果处理元件的工作负载表明它是瓶颈，则可能会增加其性能。 然而，如果包括处理元件的平台或集成电路已经在功率或热限制下运行，则性能的提高通过另一处理元件的性能的降低或上限来平衡，以保持与功率或热限制的一致性。 因此，即使在多个处理元件在功率或热限制下工作时，通过平衡功率分配来识别和缓解瓶颈。

公开(公告)号：US20140082380A1

公开(公告)日：2014-03-20

申请号：US13783986

申请日：2013-03-04

Applicant: Travis T. Schluessler ,  Ryan D. Wells ,  Yaakov Romano

Inventor： Travis T. Schluessler ,  Ryan D. Wells ,  Yaakov Romano

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, the present invention includes a processor having a first domain with a first compute engine and a second domain with a second compute engine, where each of these domains can operate at an independent voltage and frequency. A first logic may be present to update a power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a busyness of the second domain. In turn, a second logic may dynamically allocate at least a portion of a power budget for the processor between the domains based at least in part on this power bias value. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明包括处理器，其具有具有第一计算引擎的第一域和具有第二计算引擎的第二域，其中这些域中的每一个可以以独立的电压和频率工作。 可以存在第一逻辑来至少部分地基于第二域的繁忙来更新用于控制第一和第二域之间的功率的动态分配的功率偏置值。 反过来，第二逻辑可以至少部分地基于该功率偏差值来在区域之间动态分配处理器的功率预算的至少一部分。 描述和要求保护其他实施例。

公开(公告)号：US20140082378A1

公开(公告)日：2014-03-20

申请号：US13621478

申请日：2012-09-17

Applicant: Travis T. Schluessler ,  Ryan D. Wells ,  Yaakov Romano

Inventor： Travis T. Schluessler ,  Ryan D. Wells ,  Yaakov Romano

IPC: G06F1/26

CPC classification number: G06F1/26 ,  G06F1/324 ,  G06F1/3296 ,  Y02D10/126 ,  Y02D10/172

Abstract: In one embodiment, the present invention includes a processor having a first domain with a first compute engine and a second domain with a second compute engine, where each of these domains can operate at an independent voltage and frequency. A first logic may be present to update a power bias value used to control dynamic allocation of power between the first and second domains based at least in part on a busyness of the second domain. In turn, a second logic may dynamically allocate at least a portion of a power budget for the processor between the domains based at least in part on this power bias value. Other embodiments are described and claimed.

公开(公告)号：US20140036909A1

公开(公告)日：2014-02-06

申请号：US13926085

申请日：2013-06-25

Applicant: Bryan E. Veal ,  Travis T. Schluessler

Inventor： Bryan E. Veal ,  Travis T. Schluessler

IPC: H04L12/947

CPC classification number: H04L49/25 ,  G06F9/3885 ,  G06F9/3887 ,  H04L49/9094

Abstract: Executing a single instruction/multiple data (SIMD) instruction of a program to process a vector of data wherein each element of the packet vector corresponds to a different received packet.

Abstract translation: 执行程序的单指令/多数据（SIMD）指令以处理数据向量，其中分组向量的每个元素对应于不同的接收分组。

公开(公告)号：US08341369B2

公开(公告)日：2012-12-25

申请号：US13336913

申请日：2011-12-23

Applicant: Uday Savagaonkar ,  Travis T. Schluessler ,  Hormuzd Khosravi ,  Ravi Sahita ,  Gayathri Nagabhushan ,  David Durham

Inventor： Uday Savagaonkar ,  Travis T. Schluessler ,  Hormuzd Khosravi ,  Ravi Sahita ,  Gayathri Nagabhushan ,  David Durham

IPC: G06F12/00

CPC classification number: G06F12/145

Abstract: In accordance with disclosed embodiments, there are provided methods, systems, and apparatuses for implementing hardware of a virtualized processor based system detecting a specified type of memory access to an identified region of memory and in response to the detecting generating an interrupt for a virtual machine monitor (VMM) of the virtualized processor based system.

Abstract translation: 根据所公开的实施例，提供了用于实现基于虚拟处理器的系统的硬件的方法，系统和装置，该系统检测对所识别的存储器区域的指定类型的存储器访问，并且响应于该检测产生虚拟机的中断 基于虚拟化处理器的系统的监视器（VMM）。

公开(公告)号：US20120117614A1

公开(公告)日：2012-05-10

申请号：US13305902

申请日：2011-11-29

Applicant: Ravi Sahita ,  Travis T. Schluessler

Inventor： Ravi Sahita ,  Travis T. Schluessler

IPC: G06F21/00 ,  G06F9/455

CPC classification number: H04L9/3234 ,  G06F9/45558 ,  G06F12/1433 ,  G06F12/1491 ,  G06F21/53 ,  G06F21/72 ,  G06F2009/45587 ,  G06F2221/034 ,  G06F2221/2149 ,  G06F2221/2153

Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform, which includes Virtual Machine Monitor (VMM) managed components coupled to the VMM and a plurality of Virtual Machines (VMs). One of the VMM managed components is a Trusted Platform Module (TPM) Each virtual machine includes a guest Operating System, a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the TDD's memory contents. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD.

Abstract translation: 用于高性能安全访问硬件虚拟化平台上的可信平台模块的系统和方法，其包括耦合到VMM的虚拟机监视器（VMM）被管理的组件和多个虚拟机（VM）。 VMM管理的组件之一是可信平台模块（TPM）每个虚拟机包括客户操作系统，TPM设备驱动程序（TDD）和至少一个安全应用程序。 VMM在每个TDD的存储器中创建内部分区，使得VM中相同或更高特权级别的其他代码和信息不能访问TDD的存储器内容。 VMM还将来自TDD的访问映射到为VM请求访问专门指定的TPM寄存器空间。 由TDD请求的TPM的内容存储在专用的VMM管理的受保护的页表中，该表为TDD提供基于硬件的存储器隔离。

公开(公告)号：US08090919B2

公开(公告)日：2012-01-03

申请号：US11967683

申请日：2007-12-31

Applicant: Ravi Sahita ,  Travis T. Schluessler

Inventor： Ravi Sahita ,  Travis T. Schluessler

IPC: G06F12/00 ,  G06F13/00 ,  G06F13/28

CPC classification number: H04L9/3234 ,  G06F9/45558 ,  G06F12/1433 ,  G06F12/1491 ,  G06F21/53 ,  G06F21/72 ,  G06F2009/45587 ,  G06F2221/034 ,  G06F2221/2149 ,  G06F2221/2153

Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. The virtualization platform including Virtual Machine Monitor (VMM) managed components coupled to the VMM. One of the VMM managed components is a TPM (Trusted Platform Module). The virtualization platform also includes a plurality of Virtual Machines (VMs). Each of the virtual machines includes a guest Operating System (OS), a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the memory contents of the TDD. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD.

Abstract translation: 用于高性能安全访问硬件虚拟化平台上的可信平台模块的系统和方法。 虚拟化平台包括虚拟机监视器（VMM）管理的组件耦合到VMM。 其中一个VMM管理组件是TPM（可信平台模块）。 虚拟化平台还包括多个虚拟机（VM）。 每个虚拟机包括客户操作系统（OS），TPM设备驱动器（TDD）和至少一个安全应用。 VMM在每个TDD的存储器中创建内部分区，使得VM中相同或更高特权级别的其他代码和信息不能访问TDD的存储器内容。 VMM还将来自TDD的访问映射到为VM请求访问专门指定的TPM寄存器空间。 由TDD请求的TPM的内容存储在专用的VMM管理的受保护的页表中，该表为TDD提供基于硬件的存储器隔离。

公开(公告)号：US20090172328A1

公开(公告)日：2009-07-02

申请号：US11967683

申请日：2007-12-31

Applicant: Ravi Sahita ,  Travis T. Schluessler

Inventor： Ravi Sahita ,  Travis T. Schluessler

IPC: G06F12/00

CPC classification number: H04L9/3234 ,  G06F9/45558 ,  G06F12/1433 ,  G06F12/1491 ,  G06F21/53 ,  G06F21/72 ,  G06F2009/45587 ,  G06F2221/034 ,  G06F2221/2149 ,  G06F2221/2153

Abstract: A system and method for high performance secure access to a trusted platform module on a hardware virtualization platform. The virtualization platform including Virtual Machine Monitor (VMM) managed components coupled to the VMM. One of the VMM managed components is a TPM (Trusted Platform Module). The virtualization platform also includes a plurality of Virtual Machines (VMs). Each of the virtual machines includes a guest Operating System (OS), a TPM device driver (TDD), and at least one security application. The VMM creates an intra-partition in memory for each TDD such that other code and information at a same or higher privilege level in the VM cannot access the memory contents of the TDD. The VMM also maps access only from the TDD to a TPM register space specifically designated for the VM requesting access. Contents of the TPM requested by the TDD are stored in an exclusively VMM-managed protected page table that provides hardware-based memory isolation for the TDD.

Abstract translation: 用于高性能安全访问硬件虚拟化平台上的可信平台模块的系统和方法。 虚拟化平台包括虚拟机监视器（VMM）管理的组件耦合到VMM。 其中一个VMM管理组件是TPM（可信平台模块）。 虚拟化平台还包括多个虚拟机（VM）。 每个虚拟机包括客户操作系统（OS），TPM设备驱动器（TDD）和至少一个安全应用。 VMM在每个TDD的存储器中创建内部分区，使得VM中相同或更高特权级别的其他代码和信息不能访问TDD的存储器内容。 VMM还将来自TDD的访问映射到为VM请求访问专门指定的TPM寄存器空间。 由TDD请求的TPM的内容存储在专用的VMM管理的受保护的页表中，该表为TDD提供基于硬件的存储器隔离。

公开(公告)号：US20190066356A1

公开(公告)日：2019-02-28

申请号：US15693084

申请日：2017-08-31

Applicant: JOHN C. GIERACH ,  DARREL K. PALKE ,  TRAVIS T. SCHLUESSLER ,  PRASOONKUMAR SURTI

Inventor： JOHN C. GIERACH ,  DARREL K. PALKE ,  TRAVIS T. SCHLUESSLER ,  PRASOONKUMAR SURTI

IPC: G06T15/00 ,  G06T15/80 ,  G06T15/40 ,  G06T15/20

CPC classification number: G06T15/005 ,  G06T1/20 ,  G06T1/60 ,  G06T15/205 ,  G06T15/40 ,  G06T15/80 ,  G06T2200/28

Abstract: An apparatus and method for programmable depth stencil pipeline stage and shading. For example, one embodiment of a graphics processing apparatus comprises: a rasterizer to generate a plurality of pixel blocks, one or more of which overlap one or more primitives; programmable depth stencil circuitry to perform depth stencil tests on the pixels which overlap the one or more primitives to identify pixels which pass the depth stencil tests; and thread dispatch circuitry to dispatch pixel shader threads to perform pixel shading operations on those pixels which pass the depth stencil tests, the thread dispatch circuitry including thread dispatch recombine logic to combine pixels which have passed the depth stencil test from multiple pixel blocks into a set of pixel shader threads to be executed concurrently on single instruction multiple data (SIMD) hardware.