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79 条记录 (耗时 0.019 秒)

    Image decoding apparatus
    21.
    发明授权
    Image decoding apparatus 失效
    图像解码装置

    公开(公告)号：US06212236B1

    公开(公告)日：2001-04-03

    申请号：US09048190

    申请日：1998-03-25

    申请人： Hideshi Nishida ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara

    发明人： Hideshi Nishida ,  Kozo Kimura ,  Makoto Hirai ,  Tokuzo Kiyohara

    IPC分类号： H04N712

    CPC分类号： H04N19/507 ,  H04N19/61

    摘要： Bitstream analyzing unit 111 fetches a coded block pattern and a coded quantized DCT coefficient from each block in a bitstream. Entropy decoding unit 112 decodes the coded block pattern into a block pattern and decodes the coded quantized DCT coefficient into pairs of a run length and an effectiveness factor. Dequantization unit 115 generates orthogonal transformation coefficients from the pairs of a run length and an effectiveness factor. Inverse Discrete Cosine Transform (IDCT) unit 110 generates a difference image from the orthogonal transformation coefficients. Decode controlling unit 110 instructs first selecting unit 118 to select constants “0”output from first constant generating unit 117 when the image is a “skipped” block. Image storage unit 120 stores a plurality of reference frame pictures having been decoded. Image restoring unit 119 restores an original block by adding a decoded difference image to a reference block read from the reference frame pictures stored in the image storage unit 120.

    摘要翻译： 比特流分析单元111从比特流中的每个块获取编码块模式和编码的量化DCT系数。 熵解码单元112将编码块模式解码为块模式，并将编码的量化DCT系数解码为游程长度和有效性因子对。 去量化单元115从游程长度和有效性因子的对生成正交变换系数。 逆离散余弦变换（IDCT）单元110从正交变换系数生成差分图像。 当图像为“跳过”块时，解码控制单元110指示第一选择单元118选择从第一常数生成单元117输出的常数“0”。 图像存储单元120存储已被解码的多个参考帧图像。 图像恢复单元119通过将解码的差异图像添加到从存储在图像存储单元120中的参考帧图像中读取的参考块来恢复原始块。

    Pipelined data processor having combined operand fetch and execution stage to reduce number of pipeline stages and penalty associated with branch instructions
    23.
    发明授权
    Pipelined data processor having combined operand fetch and execution stage to reduce number of pipeline stages and penalty associated with branch instructions 失效
    流水线数据处理器具有组合的操作数获取和执行阶段，以减少流水线阶段的数量和与分支指令相关联的惩罚

    公开(公告)号：US5469552A

    公开(公告)日：1995-11-21

    申请号：US310627

    申请日：1994-09-22

    申请人： Masato Suzuki ,  Tokuzo Kiyohara

    发明人： Masato Suzuki ,  Tokuzo Kiyohara

    IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3861 ,  G06F9/3867

    摘要： A data processing apparatus having a pipelined architecture, includes an instruction fetch unit for fetching an instruction from a memory; an instruction decode unit for decoding the instruction fetched by the instruction fetch unit, and outputting fetch control data regarding operand fetching and operation control data regarding execution of the instruction; an execution unit for receiving the execution control data directly from the instruction decode unit, and executing a predetermined operation based on the operation control data; and an operand fetch unit for receiving the fetch control data directly from the instruction decode unit, and fetching an operand from a source other than registers in the execution unit. The operand fetch unit fetches the operand concurrently with processing in a second cycle, and subsequent cycles if any, of the operation executed by the execution unit and requiring at least two machine cycles for execution.

    摘要翻译： 具有流水线架构的数据处理装置包括用于从存储器取出指令的指令提取单元; 指令解码单元，用于对由指令获取单元取出的指令进行解码，并且输出关于操作数获取的读取控制数据和关于指令执行的操作控制数据; 执行单元，用于直接从指令解码单元接收执行控制数据，并且基于操作控制数据执行预定操作; 以及操作数取出单元，用于直接从指令解码单元接收取出控制数据，以及从除执行单元中的寄存器之外的源取得操作数。 操作数提取单元在第二个周期中与处理并行执行操作数，以及执行单元执行的操作的后续周期，并且需要至少两个机器周期执行。

    INTEGRATED CIRCUIT FOR USE IN PLASMA DISPLAY PANEL, ACCESS CONTROL METHOD, AND PLASMA DISPLAY SYSTEM
    25.
    发明申请
    INTEGRATED CIRCUIT FOR USE IN PLASMA DISPLAY PANEL, ACCESS CONTROL METHOD, AND PLASMA DISPLAY SYSTEM 有权
    用于等离子显示面板的集成电路，访问控制方法和等离子体显示系统

    公开(公告)号：US20120154414A1

    公开(公告)日：2012-06-21

    申请号：US13393349

    申请日：2011-06-09

    申请人： Masaki Maeda ,  Naoki Ootani ,  Tokuzo Kiyohara

    发明人： Masaki Maeda ,  Naoki Ootani ,  Tokuzo Kiyohara

    IPC分类号： G09G3/28 ,  G06F13/372 ,  G09G5/39

    CPC分类号： G09G3/288 ,  G09G3/2022 ,  G09G3/293 ,  G09G5/395 ,  G09G2320/103

    摘要： Provided is a plasma display system capable of restricting peak data traffic when a shared memory is used. In the plasma display system, a control unit 104 prohibits a moving picture decoder 101 from accessing a shared memory 140 while an SF reading unit 101 is reading, from the shared memory 140, SF pixel data which is information about respective cells to be lit in a plurality of subfields. On the other hand, the control unit 104 permits the moving picture decoder 101 to access the shared memory 140 while the SF reading unit 101 is not reading the SF pixel data from the shared memory 140, that is to say, during a sustain discharge period.

    摘要翻译： 提供了当使用共享存储器时能够限制峰值数据业务的等离子体显示系统。 在等离子体显示系统中，控制单元104在SF读取单元101从共享存储器140读取作为要点燃的各个单元的信息的SF像素数据的同时，禁止运动图像解码器101访问共享存储器140 多个子场。 另一方面，控制单元104允许运动图像解码器101访问共享存储器140，而SF读取单元101不从共享存储器140读取SF像素数据，即在维持放电期间 。

    External device access apparatus
    28.
    发明授权
    External device access apparatus 有权
    外部设备接入设备

    公开(公告)号：US07685351B2

    公开(公告)日：2010-03-23

    申请号：US11916319

    申请日：2006-06-06

    申请人： Takao Kawakami ,  Masaitsu Nakajima ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Nobuo Higaki ,  Yousuke Kudo

    发明人： Takao Kawakami ,  Masaitsu Nakajima ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Nobuo Higaki ,  Yousuke Kudo

    IPC分类号： G06F13/00

    CPC分类号： G06F13/385

    摘要： In response to a write request from a master to write to an external device, a control unit holds a write address and write data from the master in a write address holding unit and in a write data holding unit, respectively, outputs a reception signal to the master, and writes the write data to the external device specified by the write address. When the master holds the read address in the read address holding unit, the control unit reads data from the external device specified by the read address, and holds the read data in the read data holding unit.

    摘要翻译： 响应于来自主机对外部设备的写入请求，控制单元分别保存写入地址并从写入地址保存单元和写入数据保持单元中写入数据，将接收信号输出到 并将写入数据写入由写入地址指定的外部设备。 当主机在读取地址保持单元中保持读取地址时，控制单元从读取地址指定的外部设备读取数据，并将读取的数据保存在读取数据保存单元中。

    ARBITRATION DEVICE FOR ARBITRATING AMONG A PLURALITY OF MASTER DEVICES, ARBITRATION METHOD, AND VIDEO PROCESSING DEVICE INCLUDING THE ARBITRATION DEVICE
    29.
    发明申请
    ARBITRATION DEVICE FOR ARBITRATING AMONG A PLURALITY OF MASTER DEVICES, ARBITRATION METHOD, AND VIDEO PROCESSING DEVICE INCLUDING THE ARBITRATION DEVICE 有权
    用于仲裁大量设备的仲裁设备，仲裁方法和包括仲裁设备的视频处理设备

    公开(公告)号：US20100005209A1

    公开(公告)日：2010-01-07

    申请号：US12559916

    申请日：2009-09-15

    申请人： Tetsuji Mochida ,  Tokuzo Kiyohara ,  Takashi Yamada

    发明人： Tetsuji Mochida ,  Tokuzo Kiyohara ,  Takashi Yamada

    IPC分类号： G06F13/366

    CPC分类号： G06F13/1605

    摘要： An arbitration device arbitrates among master devices such that each master device is allowed to access a shared memory at a predetermined bandwidth, and the arbitration device permits an access request in a first period that a designer has set as desired if the access request has been made by a specific master device beyond a bandwidth that has been allocated in advance. The arbitration device masks an access request from the specific master device in a second period that follows the first period.

    摘要翻译： 仲裁装置在主设备之间进行仲裁，使得允许每个主设备以预定带宽访问共享存储器，并且仲裁设备允许设计者在已经设置了访问请求的第一时段中设置访问请求 通过特定的主设备超出已预先分配的带宽。 仲裁设备在跟随第一周期的第二周期中屏蔽来自特定主设备的访问请求。