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    Pipelined data processor having combined operand fetch and execution stage to reduce number of pipeline stages and penalty associated with branch instructions
    1.
    发明授权
    Pipelined data processor having combined operand fetch and execution stage to reduce number of pipeline stages and penalty associated with branch instructions 失效
    流水线数据处理器具有组合的操作数获取和执行阶段，以减少流水线阶段的数量和与分支指令相关联的惩罚

    公开(公告)号：US5469552A

    公开(公告)日：1995-11-21

    申请号：US310627

    申请日：1994-09-22

    申请人： Masato Suzuki ,  Tokuzo Kiyohara

    发明人： Masato Suzuki ,  Tokuzo Kiyohara

    IPC分类号： G06F7/00 ,  G06F9/38 ,  G06F9/30

    CPC分类号： G06F9/3861 ,  G06F9/3867

    摘要： A data processing apparatus having a pipelined architecture, includes an instruction fetch unit for fetching an instruction from a memory; an instruction decode unit for decoding the instruction fetched by the instruction fetch unit, and outputting fetch control data regarding operand fetching and operation control data regarding execution of the instruction; an execution unit for receiving the execution control data directly from the instruction decode unit, and executing a predetermined operation based on the operation control data; and an operand fetch unit for receiving the fetch control data directly from the instruction decode unit, and fetching an operand from a source other than registers in the execution unit. The operand fetch unit fetches the operand concurrently with processing in a second cycle, and subsequent cycles if any, of the operation executed by the execution unit and requiring at least two machine cycles for execution.

    摘要翻译： 具有流水线架构的数据处理装置包括用于从存储器取出指令的指令提取单元; 指令解码单元，用于对由指令获取单元取出的指令进行解码，并且输出关于操作数获取的读取控制数据和关于指令执行的操作控制数据; 执行单元，用于直接从指令解码单元接收执行控制数据，并且基于操作控制数据执行预定操作; 以及操作数取出单元，用于直接从指令解码单元接收取出控制数据，以及从除执行单元中的寄存器之外的源取得操作数。 操作数提取单元在第二个周期中与处理并行执行操作数，以及执行单元执行的操作的后续周期，并且需要至少两个机器周期执行。

    Two-dimensional filter arithmetic device and method
    3.
    发明授权
    Two-dimensional filter arithmetic device and method 有权
    二维滤波算术装置及方法

    公开(公告)号：US08260075B2

    公开(公告)日：2012-09-04

    申请号：US12097994

    申请日：2006-11-21

    申请人： Akihiko Inoue ,  Tokuzo Kiyohara

    发明人： Akihiko Inoue ,  Tokuzo Kiyohara

    IPC分类号： G06K9/00

    CPC分类号： G06T3/4007 ,  G06T2200/28 ,  H04N19/82

    摘要： A two-dimensional filter arithmetic device comprises a picture memory, a line memory, a vertical filtering unit which includes nine first filter modules installed in parallel, a buffer for timing adjustments, and a horizontal filtering unit which includes four second filter modules installed in parallel. From the line memory, the pixel values of nine full pels per line are inputted in parallel to the vertical filtering unit, nine vertically-filtered values of half pels are generated and inputted to the horizontal filtering unit; thereby, four two-dimensionally-filtered values of half pels are generated.

    摘要翻译： 二维滤波器运算装置包括图像存储器，行存储器，垂直滤波单元，其包括并联安装的九个第一滤波器模块，用于定时调整的缓冲器和包括并联安装的四个第二滤波器模块的水平滤波单元 。 从行存储器中，与垂直滤波单元并行地输入每行9个全像素的像素值，生成半个像素的九个垂直滤波值并输入到水平滤波单元; 从而产生半个像素的四维二维滤波值。

    Processor capable of reconfiguring a logical circuit
    4.
    发明授权
    Processor capable of reconfiguring a logical circuit 有权
    能够重新配置逻辑电路的处理器

    公开(公告)号：US07926055B2

    公开(公告)日：2011-04-12

    申请号：US11574359

    申请日：2006-04-12

    申请人： Hiroyuki Morishita ,  Takashi Hashimoto ,  Tokuzo Kiyohara

    发明人： Hiroyuki Morishita ,  Takashi Hashimoto ,  Tokuzo Kiyohara

    IPC分类号： G06F9/46

    CPC分类号： G06F15/7867 ,  G06F9/30076 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/3885 ,  G06F9/3897

    摘要： The present invention provides a processor that cyclically executes a plurality of threads in accordance with an execution time allocated to each of the threads, comprising a reconfigurable integrated circuit. The processor stores circuit configuration information sets respectively corresponding to the plurality of threads, reconfigures a part of the integrated circuit based on the circuit configuration information sets, and sequentially executes each thread using the integrated circuit that has been reconfigured based on one of the configuration information sets that corresponds to the thread. While executing a given thread, the processor selects a thread to be executed next, and reconfigures a part of the integrated circuit where is not currently used for execution of the given thread, based on a circuit configuration information set corresponding to the selected thread.

    摘要翻译： 本发明提供了一种根据分配给每个线程的执行时间循环地执行多个线程的处理器，包括可重构集成电路。 处理器存储分别对应于多个线程的电路配置信息集合，基于电路配置信息集重配置集成电路的一部分，并且使用基于配置信息之一重新配置的集成电路来顺序地执行每个线程 设置对应于线程。 在执行给定的线程的同时，处理器根据与所选择的线程对应的电路配置信息，选择要执行的线程，并重新配置当前不用于执行给定线程的集成电路的一部分。

    PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION
    6.
    发明申请
    PROCESSOR AND PROGRAM EXECUTION METHOD CAPABLE OF EFFICIENT PROGRAM EXECUTION 有权
    能够有效执行计划的执行者和计划执行方法

    公开(公告)号：US20080215858A1

    公开(公告)日：2008-09-04

    申请号：US12110539

    申请日：2008-04-28

    申请人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

    发明人： Kazuya Furukawa ,  Tetsuya Tanaka ,  Nobuo Higaki ,  Kunihiko Hayashi ,  Hiroshi Kadota ,  Tokuzo Kiyohara ,  Kozo Kimura ,  Hideshi Nishida ,  Kazushi Kurata ,  Shigeki Fujii ,  Toshio Sugimura

    IPC分类号： G06F9/30

    CPC分类号： G06F9/4881 ,  G06F9/3851 ,  G06F9/3867 ,  G06F9/462

    摘要： A processor for sequentially executing a plurality of programs using a plurality of register value groups stored in a memory that correspond one-to-one with the programs. The processor includes a plurality of register groups; a select/switch unit operable to select one of the plurality of register groups as an execution target register group on which a program execution is based, and to switch the selection target every time a first predetermined period elapses; a restoring unit operable to restore, every time the switching is performed, one of the register value groups into one of the register groups that is not selected as the execution target register group; a saving unit operable to save, prior to the restoring, register values in the register group targeted for restoring, by overwriting a register value group in the memory that corresponds to the register values; and a program execution unit operable to execute, every time the switching is performed, a program corresponding to a register value group in the execution target register group.

    摘要翻译： 一种处理器，用于使用存储在与所述程序一对一的存储器中的多个寄存器值组来顺序地执行多个程序。 处理器包括多个寄存器组; 选择/切换单元，其可操作以选择所述多个寄存器组中的一个作为程序执行所基于的执行目标寄存器组，并且每当经过第一预定时间时切换所述选择目标; 恢复单元，其可操作以在每次执行切换时将所述寄存器值组中的一个恢复为未被选择为所述执行目标寄存器组的寄存器组之一; 保存单元，其可操作以通过重写与寄存器值相对应的存储器中的寄存器值组来在恢复之前保存用于恢复的寄存器组中的值; 以及程序执行单元，其可操作以在每次执行切换时执行与执行目标寄存器组中的寄存器值组相对应的程序。

    Integated Circuit For Video/Audio Processing
    8.
    发明申请
    Integated Circuit For Video/Audio Processing 有权
    用于视频/音频处理的整数电路

    公开(公告)号：US20070286275A1

    公开(公告)日：2007-12-13

    申请号：US10599494

    申请日：2005-04-01

    申请人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

    发明人： Kozo Kimura ,  Tokuzo Kiyohara ,  Hiroshi Mizuno ,  Junji Michiyama ,  Tomohiko Kitamura ,  Ryoji Yamaguchi ,  Manabu Kuroda ,  Nobuhiko Yamada ,  Hideyuki Ohgose ,  Akifumi Yamana

    IPC分类号： H04B1/66 ,  G06F13/12

    CPC分类号： G06F13/4027 ,  H04N5/775 ,  H04N5/781 ,  H04N5/85 ,  H04N5/907 ,  H04N9/7921 ,  H04N9/8042

    摘要： The present invention provides an integrated circuit for video/audio processing in which the design resources obtained by the development of video/audio devices can be used also for other types of video/audio devices. The integrated circuit comprises a microcomputer block 2 including a CPU, a stream I/O block 4 for inputting/outputting video and audio streams to and from an external device, a media processing block 3 for executing the media processing including at least one of the compression and decompression of the video and audio streams, etc. inputted to the stream I/O block 4, an AV IO block 5 for converting the video and audio streams subjected to the media processing in the media processing block 3 into video and audio signals and outputting these signals to the external device, etc, and a memory IF block 6 for controlling the data transfer between the microcomputer block 2, the stream I/C block 4, the media processing block 3 and the AV IO block 5 and an external memory 9.

    摘要翻译： 本发明提供了一种用于视频/音频处理的集成电路，其中通过开发视频/音频设备获得的设计资源也可以用于其他类型的视频/音频设备。 该集成电路包括一个包括CPU的微处理器块2，用于向外部设备输入/输出视频和音频流的流I / O块4，用于执行媒体处理的媒体处理块3，包括至少一个 输入到流I / O块4的视频和音频流等的压缩和解压缩，用于将经过媒体处理块3中的媒体处理的视频和音频流转换成视频和音频信号的AV IO块5 并将这些信号输出到外部设备等;以及存储器IF块6，用于控制微计算机块2，流I / C块4，媒体处理块3和AV IO块5之间的数据传输，以及外部 记忆9。

    Cache memory and cache memory control method
    9.
    发明申请
    Cache memory and cache memory control method 审中-公开
    缓存内存和缓存内存控制方式

    公开(公告)号：US20070028055A1

    公开(公告)日：2007-02-01

    申请号：US10571531

    申请日：2004-08-23

    申请人： Tetsuya Tanaka ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Keishi Chikamura

    发明人： Tetsuya Tanaka ,  Ryuta Nakanishi ,  Tokuzo Kiyohara ,  Hiroyuki Morishita ,  Keishi Chikamura

    IPC分类号： G06F12/00

    CPC分类号： G06F12/127 ,  G06F12/124

    摘要： A cache memory of the present invention includes: for each cache entry, way 0 to way 3 which hold use flags U indicating whether or not the use flags U have been accessed; and a control unit which: updates, when a cache entry is hit, a use flag U corresponding to the hit cache entry so that the use flag U indicates that the cache entry has been accessed; and reset, in the case where all other use flags in the same set indicates that the cache entries have been accessed herein, the all other use flags so that the use flags indicate that the cache entries have not been accessed; and select a cache entry to be replaced from among the cache entries corresponding to the use flags indicating that the cache entries have not been accessed.

    摘要翻译： 本发明的高速缓存存储器包括：对于每个高速缓存条目，方式0到路径3，其保持使用标志U，指示是否已经访问了使用标志U; 以及控制单元，其在高速缓存条目被命中时更新与所述命中高速缓存条目对应的使用标志U，使得所述使用标志U指示所述高速缓存条目已经被访问; 并且在同一集合中的所有其他使用标志指示已经在这里访问了高速缓存条目的情况下，复位所有其他使用标志，使得使用标志指示高速缓存条目未被访问; 并且从与指示高速缓存条目未被访问的使用标志相对应的高速缓存条目中选择要替换的高速缓存条目。

    Transcoder
    10.
    发明授权
    Transcoder 失效
    转码器

    公开(公告)号：US07167520B2

    公开(公告)日：2007-01-23

    申请号：US10686237

    申请日：2003-10-15

    申请人： Kosuke Yoshioka ,  Makoto Hirai ,  Tetsuji Mochida ,  Hiroyuki Oka ,  Hideshi Nishida ,  Tokuzo Kiyohara

    发明人： Kosuke Yoshioka ,  Makoto Hirai ,  Tetsuji Mochida ,  Hiroyuki Oka ,  Hideshi Nishida ,  Tokuzo Kiyohara

    IPC分类号： H04B1/66

    CPC分类号： G06T3/40 ,  H04N19/16 ,  H04N19/40 ,  H04N19/42 ,  H04N19/59 ,  H04N19/61

    摘要： A transcoder for resizing video data and outputting the resized video data to a reproduction apparatus. The reproduction apparatus reproduces the resized video data by repeating a display period and a non-display period alternately. The transcoder includes: a resizing unit that resizes the video data; and a control unit that causes the resizing unit to resize the video data to first video data having a first resolution so that the reproduction apparatus displays one image during each display period, and causes the resizing unit to resize, during each period between the resizing of the video data to the first video data, the video data to second video data having a second resolution that is lower than the first resolution.

    摘要翻译： 一种用于调整视频数据大小并将调整大小的视频数据输出到再现设备的代码转换器。 再现装置通过重复显示周期和非显示周期交替地再现调整大小的视频数据。 代码转换器包括：调整大小的视频数据的调整大小; 以及控制单元，其使所述调整大小单元将所述视频数据的大小调整为具有第一分辨率的第一视频数据，使得所述再现设备在每个显示周期期间显示一个图像，并且使得调整大小单元在调整大小 将视频数据提供给第一视频数据，将视频数据转换为具有低于第一分辨率的第二分辨率的第二视频数据。