公开(公告)号：US08288766B2

公开(公告)日：2012-10-16

申请号：US12555824

申请日：2009-09-09

Applicant: Je-Hun Lee ,  Ki-Won Kim ,  Do-Hyun Kim ,  Woo-Geun Lee ,  Kap-Soo Yoon

Inventor： Je-Hun Lee ,  Ki-Won Kim ,  Do-Hyun Kim ,  Woo-Geun Lee ,  Kap-Soo Yoon

IPC: H01L29/10

CPC classification number: H01L27/1225 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Abstract translation: TFT阵列基板包括设置在绝缘基板上并包括沟道部分的半导体氧化物层，与半导体氧化物层重叠的栅极电极，插入在半导体氧化物层和栅电极之间的栅极绝缘层，以及设置在 半导体氧化物层和栅电极。 栅极绝缘层和钝化层中的至少一个包括氧氮化物层，并且氧氮化物层在氧氮化物层的位置更靠近半导体氧化物层的位置处具有比氮的浓度高的氧氮化物层。

公开(公告)号：US20120228604A1

公开(公告)日：2012-09-13

申请号：US13400931

申请日：2012-02-21

Applicant: Seung-Ha CHOI ,  Sung Haeng CHO ,  Woo Geun LEE ,  Kap Soo YOON ,  Sho Yeon KIM

Inventor： Seung-Ha CHOI ,  Sung Haeng CHO ,  Woo Geun LEE ,  Kap Soo YOON ,  Sho Yeon KIM

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/7869 ,  H01L27/1225 ,  H01L27/1288

Abstract: A thin film transistor array panel includes a gate electrode on an insulating substrate, a gate insulating layer on the gate electrode, a semiconductor on the gate insulating layer, a thin film transistor including a source electrode and a drain electrode on the oxide semiconductor, and a pixel electrode which is connected to the drain electrode. The semiconductor includes a first layer having a relatively low fluorine content and a second layer having a relatively high fluorine content. The second layer of the semiconductor is only between the first layer of the semiconductor and the source electrode, and between the first layer of the semiconductor and the drain electrode.

Abstract translation: 薄膜晶体管阵列面板包括绝缘基板上的栅极电极，栅电极上的栅极绝缘层，栅极绝缘层上的半导体，氧化物半导体上包括源电极和漏电极的薄膜晶体管，以及 连接到漏电极的像素电极。 半导体包括具有相对低的氟含量的第一层和具有相对高的氟含量的第二层。 半导体的第二层仅在半导体的第一层和源电极之间以及半导体的第一层和漏电极之间。

公开(公告)号：US20120146029A1

公开(公告)日：2012-06-14

申请号：US13185105

申请日：2011-07-18

Applicant: Young Joo CHOI ,  Woo Geun LEE ,  Kap Soo YOON ,  Ki-Won KIM ,  Sang Wan JIN ,  Jae Won SONG ,  Zhu Xun

Inventor： Young Joo CHOI ,  Woo Geun LEE ,  Kap Soo YOON ,  Ki-Won KIM ,  Sang Wan JIN ,  Jae Won SONG ,  Zhu Xun

IPC: H01L29/786

CPC classification number: H01L27/1225 ,  G02F1/1368 ,  H01L29/41733 ,  H01L29/4908

Abstract: A thin film transistor array panel includes an insulating substrate, a gate line disposed on the insulating substrate having a gate electrode, a first gate insulating layer disposed on the gate line and made of silicon nitride, a second gate insulating layer disposed on the first gate insulating layer and made of silicon oxide, an oxide semiconductor disposed on the second gate insulating layer, a data line disposed on the oxide semiconductor and having a source electrode, a drain electrode disposed on the oxide semiconductor and facing the source electrode, and a pixel electrode that is connected to the drain electrode. A thickness of the second gate insulating layer may range from 200 Å to less than 500 Å.

Abstract translation: 薄膜晶体管阵列面板包括绝缘基板，设置在具有栅电极的绝缘基板上的栅极线，设置在栅极线上并由氮化硅制成的第一栅极绝缘层，设置在第一栅极上的第二栅极绝缘层 绝缘层，由氧化硅制成，设置在第二栅极绝缘层上的氧化物半导体，设置在氧化物半导体上的数据线，具有源电极，设置在氧化物半导体上并面对源电极的漏极，以及像素 连接到漏电极的电极。 第二栅极绝缘层的厚度可以在200至小于500的范围内。

公开(公告)号：US08174020B2

公开(公告)日：2012-05-08

申请号：US12556277

申请日：2009-09-09

Applicant: Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

Inventor： Young-Wook Lee ,  Hong-Suk Yoo ,  Jean-Ho Song ,  Jae-Hyoung Youn ,  Woo-Geun Lee ,  Ki-Won Kim ,  Jong-In Kim

IPC: H01L27/14

CPC classification number: H01L29/66742 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1248

Abstract: A thin film transistor substrate according to an embodiment of the present invention includes: an insulation substrate; a gate line formed on the insulation substrate; a first interlayer insulating layer formed on the gate line; a data line and a gate electrode formed on the first interlayer insulating layer; a gate insulating layer formed on the data line and gate electrode; a semiconductor formed on the gate insulating layer and overlapping the gate electrode; a second interlayer insulating layer formed on the semiconductor; a first connection formed on the second interlayer insulating layer and electrically connecting the gate line and the gate electrode to each other; a drain electrode connected to the semiconductor; a pixel electrode connected to the drain electrode; and a second connection connecting the data line and the semiconductor to each other.

Abstract translation: 根据本发明实施例的薄膜晶体管基板包括：绝缘基板; 形成在所述绝缘基板上的栅极线; 形成在栅极线上的第一层间绝缘层; 形成在所述第一层间绝缘层上的数据线和栅电极; 形成在数据线和栅电极上的栅极绝缘层; 形成在栅极绝缘层上并与栅电极重叠的半导体; 形成在所述半导体上的第二层间绝缘层; 形成在所述第二层间绝缘层上并将所述栅极线和所述栅电极彼此电连接的第一连接; 连接到半导体的漏电极; 连接到所述漏电极的像素电极; 以及将数据线和半导体彼此连接的第二连接。

公开(公告)号：US08144280B2

公开(公告)日：2012-03-27

申请号：US12152619

申请日：2008-05-14

Applicant: Woo-Geun Lee ,  Shi-Yul Kim ,  Jae-Hyoung Youn ,  Young-Wook Lee

Inventor： Woo-Geun Lee ,  Shi-Yul Kim ,  Jae-Hyoung Youn ,  Young-Wook Lee

IPC: G02F1/136 ,  G02F1/1343

CPC classification number: G02F1/136286 ,  G02F1/136209 ,  G02F2001/13606 ,  G02F2001/136218 ,  G02F2001/136222 ,  G02F2201/40

Abstract: A liquid crystal display to prevent light leakage with an improvement of aperture ratio and a reduction of load of a data line is provided. The liquid crystal display includes a gate line and a storage electrode line formed on a insulating substrate and apart from each other, a first data line and a second data line intersecting the gate line, a first pixel electrode defined by the gate line and the first data line, and a second pixel electrode defined by the gate line and the second data line and neighboring the first pixel electrode. Also, a blocking electrode between the first pixel electrode and the second pixel electrode is included, wherein at least portion of the first data line is disposed under the first pixel electrode, and at least portion of the blocking electrode is disposed under the second pixel electrode and apart from the first data line.

Abstract translation: 提供了一种液晶显示器，用于防止光泄漏，同时提高了开口率和减少了数据线的负载。 液晶显示器包括形成在绝缘基板上并且彼此分开的栅极线和存储电极线，与栅极线相交的第一数据线和第二数据线，由栅极线和第一栅极线限定的第一像素电极 数据线和由栅极线和第二数据线限定并与第一像素电极相邻的第二像素电极。 此外，包括第一像素电极和第二像素电极之间的阻挡电极，其中第一数据线的至少一部分设置在第一像素电极下方，并且阻挡电极的至少一部分设置在第二像素电极下方 并且除了第一条数据线之外。

公开(公告)号：US20120037906A1

公开(公告)日：2012-02-16

申请号：US13115088

申请日：2011-05-24

Applicant: Hye-Young RYU ,  Woo-Geun LEE ,  Young-Joo CHOI ,  Kyoung-Jae CHUNG ,  Jin-Won LEE ,  Seung-Ha CHOI ,  Hee-Jun BYEON ,  Pil-Sang YUN

Inventor： Hye-Young RYU ,  Woo-Geun LEE ,  Young-Joo CHOI ,  Kyoung-Jae CHUNG ,  Jin-Won LEE ,  Seung-Ha CHOI ,  Hee-Jun BYEON ,  Pil-Sang YUN

IPC: H01L29/786 ,  H01L21/44

CPC classification number: H01L27/1214 ,  H01L27/1225 ,  H01L27/1255

Abstract: A thin film transistor array substrate capable of reducing degradation of a device due to degradation of an oxide semiconductor pattern and a method of fabricating the same are provided. The thin film transistor array substrate may include an insulating substrate on which a gate electrode is formed, a gate insulating film formed on the insulating substrate, an oxide semiconductor pattern disposed on the gate insulating film, an anti-etching pattern formed on the oxide semiconductor pattern, and a source electrode and a drain electrode formed on the anti-etching pattern. The oxide semiconductor pattern may include an edge portion positioned between the source electrode and the drain electrode, and the edge portion may include at least one conductive region and at least one non-conductive region.

Abstract translation: 提供了能够降低由于氧化物半导体图案的劣化引起的器件劣化的薄膜晶体管阵列基板及其制造方法。 薄膜晶体管阵列基板可以包括其上形成有栅极的绝缘基板，形成在绝缘基板上的栅极绝缘膜，设置在栅极绝缘膜上的氧化物半导体图案，形成在氧化物半导体上的抗蚀刻图案 图案，以及形成在防蚀刻图案上的源电极和漏电极。 氧化物半导体图案可以包括位于源电极和漏电极之间的边缘部分，并且边缘部分可以包括至少一个导电区域和至少一个非导电区域。

公开(公告)号：US20110227063A1

公开(公告)日：2011-09-22

申请号：US13046130

申请日：2011-03-11

Applicant: Pil-Sang YUN ,  Young-Wook LEE ,  Woo-Geun LEE

Inventor： Pil-Sang YUN ,  Young-Wook LEE ,  Woo-Geun LEE

IPC: H01L29/786 ,  H01L33/00

CPC classification number: H01L21/467 ,  H01L27/1214 ,  H01L27/1225 ,  H01L27/124 ,  H01L29/41733 ,  H01L29/7869

Abstract: Provided is an oxide thin-film transistor (TFT) substrate that may enhance the display quality of a display device and a method of fabricating the same via a simple process. The oxide TFT substrate includes: a substrate, a gate line, a data line, an oxide TFT, and a pixel electrode. An oxide layer of the oxide TFT includes a first region that has semiconductor characteristics and a channel, and a second region that is conductive and surrounds the first region. A portion of the first region is electrically connected to the pixel electrode, and the second region is electrically connected to the data line.

Abstract translation: 提供了可以通过简单的处理来提高显示装置的显示质量的氧化物薄膜晶体管（TFT）基板及其制造方法。 氧化物TFT基板包括：基板，栅极线，数据线，氧化物TFT和像素电极。 氧化物TFT的氧化物层包括具有半导体特性的第一区域和沟道，以及导电并围绕第一区域的第二区域。 第一区域的一部分电连接到像素电极，并且第二区域电连接到数据线。

公开(公告)号：US07888675B2

公开(公告)日：2011-02-15

申请号：US12099718

申请日：2008-04-08

Applicant: Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

Inventor： Sang-Gab Kim ,  Woo-Geun Lee ,  Shi-Yul Kim ,  Jin-Ho Ju ,  Jang-Soo Kim ,  Sang-Woo Whangbo ,  Min-Seok Oh ,  Hye-Young Ryu ,  Hong-Kee Chin

IPC: H01L21/00

CPC classification number: H01L27/124 ,  G02F2001/13629 ,  H01L29/458

Abstract: The present invention provides a manufacturing method of a thin film transistor array panel, which includes forming a gate line on a substrate; forming a gate insulating layer, a semiconductor layer, and an ohmic contact on the gate line; forming a first conducting film including Mo, a second conducting film including Al, and a third conducting film including Mo on the ohmic contact; forming a first photoresist pattern on the third conducting film; etching the first, second, and third conducting films, the ohmic contact, and the semiconductor layer using the first photoresist pattern as a mask; removing the first photoresist pattern by a predetermined thickness to form a second photoresist pattern; etching the first, second, and third conducting films using the second photoresist pattern as a mask to expose a portion of the ohmic contact; and etching the exposed ohmic contact using a Cl-containing gas and a F-containing gas.

Abstract translation: 本发明提供一种薄膜晶体管阵列面板的制造方法，其包括在基板上形成栅极线; 在栅极线上形成栅极绝缘层，半导体层和欧姆接触; 形成包括Mo的第一导电膜，包括Al的第二导电膜和在欧姆接触上包含Mo的第三导电膜; 在所述第三导电膜上形成第一光致抗蚀剂图案; 使用第一光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜，欧姆接触和半导体层; 将第一光致抗蚀剂图案去除预定厚度以形成第二光致抗蚀剂图案; 使用第二光致抗蚀剂图案作为掩模蚀刻第一，第二和第三导电膜以暴露欧姆接触的一部分; 并使用含Cl气体和含F气体蚀刻暴露的欧姆接触。

公开(公告)号：US20100133539A1

公开(公告)日：2010-06-03

申请号：US12571345

申请日：2009-09-30

Applicant: Hoon KANG ,  Yun-Seok Lee ,  Jae-Sung Kim ,  Yang-Ho Jung ,  Young-Je Cho ,  Cheon-Jae Maeng ,  Woo-Geun Lee

Inventor： Hoon KANG ,  Yun-Seok Lee ,  Jae-Sung Kim ,  Yang-Ho Jung ,  Young-Je Cho ,  Cheon-Jae Maeng ,  Woo-Geun Lee

IPC: H01L29/40 ,  H01L21/77

CPC classification number: H01L29/78642 ,  H01L27/12 ,  H01L29/42384

Abstract: Provided is a thin-film transistor (TFT) substrate. The TFT substrate includes: an insulating substrate; a semiconductor pattern which is formed on the insulating substrate, the semiconductor pattern having a top surface and a bottom surface; a source electrode and a drain electrode which are disposed on the top and bottom surfaces of the semiconductor pattern, respectively; a gate electrode which is disposed alongside the semiconductor pattern with a gate insulating film interposed therebetween; a data line which is connected to the source electrode and extends in a first direction; a gate line which is connected to the gate electrode and extends in a second direction; and a pixel electrode which is connected to the drain electrode and is formed in a pixel region.

Abstract translation: 提供了薄膜晶体管（TFT）基板。 TFT基板包括：绝缘基板; 形成在所述绝缘基板上的半导体图案，所述半导体图案具有顶面和底面; 源电极和漏电极，分别设置在半导体图案的顶表面和底表面上; 栅极电极，其间设置有栅极绝缘膜并且位于半导体图案的旁边; 数据线，其连接到所述源电极并沿第一方向延伸; 栅极线，其连接到所述栅电极并沿第二方向延伸; 以及连接到漏电极并形成在像素区域中的像素电极。

公开(公告)号：US20100065841A1

公开(公告)日：2010-03-18

申请号：US12555824

申请日：2009-09-09

Applicant: Je-Hun LEE ,  Ki-Won KIM ,  Do-Hyun KIM ,  Woo-Geun LEE ,  Kap-Soo YOON

Inventor： Je-Hun LEE ,  Ki-Won KIM ,  Do-Hyun KIM ,  Woo-Geun LEE ,  Kap-Soo YOON

IPC: H01L29/786 ,  H01L21/34

CPC classification number: H01L27/1225 ,  H01L21/0214 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02554 ,  H01L21/02565 ,  H01L23/53238 ,  H01L27/124 ,  H01L27/1248 ,  H01L27/1262 ,  H01L29/45 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66969 ,  H01L29/78603 ,  H01L29/7869 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A TFT array substrate includes a semiconductive oxide layer disposed on an insulating substrate and including a channel portion, a gate electrode overlapping the semiconductive oxide layer, a gate insulating layer interposed between the semiconductive oxide layer and the gate electrode, and a passivation layer disposed on the semiconductive oxide layer and the gate electrode. At least one of the gate insulating layer and the passivation layer includes an oxynitride layer, and the oxynitride layer has a higher concentration of oxygen than that of nitrogen in a location of the oxynitride layer closer to the semiconductive oxide layer.

Abstract translation: TFT阵列基板包括设置在绝缘基板上并包括沟道部分的半导体氧化物层，与半导体氧化物层重叠的栅极电极，插入在半导体氧化物层和栅电极之间的栅极绝缘层，以及设置在 半导体氧化物层和栅电极。 栅极绝缘层和钝化层中的至少一个包括氧氮化物层，并且氧氮化物层在氧氮化物层的位置更靠近半导体氧化物层的位置处具有比氮的浓度高的氧氮化物层。