Method and system for reducing required storage during decompression of a compressed file
    22.
    发明授权
    Method and system for reducing required storage during decompression of a compressed file 失效
    在压缩文件解压缩期间减少所需存储的方法和系统

    公开(公告)号:US07924183B2

    公开(公告)日:2011-04-12

    申请号:US12464628

    申请日:2009-05-12

    CPC classification number: G06F17/30067

    Abstract: A method and system for decompressing a compressed file is disclosed in this invention, the method comprising: reading a compressed data block from the compressed file; decompressing the compressed data block; outputting the decompressed data for storage into a decompressed file; deleting the compressed data block that was decompressed from the compressed file. The proposed method and system in this invention can reduce the unnecessary repeated data between compressed data and decompressed data. The storage space requirement will be reduced during decompression, and the existing compression/decompression algorithms need not be changed by using this invention. Thus, this invention is easy to be integrated into existing compression/decompression tools.

    Abstract translation: 在本发明中公开了一种解压缩压缩文件的方法和系统,该方法包括:从压缩文件读取压缩数据块; 解压缩压缩数据块; 将解压缩的数据输出到解压缩文件中; 删除从压缩文件解压缩的压缩数据块。 本发明提出的方法和系统可以减少压缩数据和解压缩数据之间不必要的重复数据。 在解压缩期间存储空间需求将减少,并且现有的压缩/解压缩算法不需要通过使用本发明来改变。 因此,本发明易于集成到现有的压缩/减压工具中。

    Word Line Decoder Circuit Apparatus and Method
    23.
    发明申请
    Word Line Decoder Circuit Apparatus and Method 有权
    字线解码器电路设备及方法

    公开(公告)号:US20110069571A1

    公开(公告)日:2011-03-24

    申请号:US12816960

    申请日:2010-06-16

    CPC classification number: G11C16/16

    Abstract: One embodiment of the technology is an apparatus, a memory integrated circuit. The memory integrated circuit has word line address decoding circuitry. The circuit allows selection of a single word line to have an erase voltage. A decoder circuit includes an inverter and logic. The inverter has an input, and an output controlling a word line to perform the erase operation. A voltage range of the input extends between a first voltage reference and a second voltage reference. Examples of voltages references are a voltage supply and a ground. In some embodiments, this wide voltage range results from the input being free of a threshold voltage drop from preceding circuitry limiting the voltage range of the input. The logic of the decoder is circuit is controlled by a word line address to determine a value of the input of the inverter during the erase operation.

    Abstract translation: 该技术的一个实施例是一种装置,存储器集成电路。 存储器集成电路具有字线地址解码电路。 该电路允许选择单个字线以具有擦除电压。 解码器电路包括反相器和逻辑。 逆变器具有输入和控制字线的输出以执行擦除操作。 输入的电压范围在第一参考电压和第二电压基准之间延伸。 电压基准的示例是电压源和地。 在一些实施例中,该宽电压范围来自于输入端没有来自限制输入的电压范围的前一电路的阈值电压降。 解码器的逻辑电路由字线地址控制,以在擦除操作期间确定反相器的输入值。

    Absolute time delay generating device
    24.
    发明授权
    Absolute time delay generating device 有权
    绝对延时发生装置

    公开(公告)号:US07825713B2

    公开(公告)日:2010-11-02

    申请号:US12286765

    申请日:2008-10-02

    CPC classification number: G06F1/14

    Abstract: An absolute time delay generating device includes a PVT (process-voltage-temperature) detection device and a delay-timing generator. The PVT detection device includes at least a delay module and a signal phase/frequency control module. The delay module includes a control unit and a reference unit. The control unit differs from the reference unit in sensitivity of delay property to PVT. The delay module compares phase or frequency differences generated when origin signals pass through the control unit and reference unit respectively, and produce delay parameters of the delay module. The signal phase/frequency control module receives and compares the delay parameters to determine an ambient PVT condition for the absolute time delay generating device, so as to control and correct the delay-timing generator and thereby generate accurate absolute time delay. Under various PVT influences, the absolute time delay generating device is capable of generating accurate, absolute time signals.

    Abstract translation: 绝对时间延迟产生装置包括PVT(过程电压 - 温度)检测装置和延迟定时发生器。 PVT检测装置至少包括延迟模块和信号相位/频率控制模块。 延迟模块包括控制单元和参考单元。 控制单元与PVT的延迟属性的灵敏度不同于参考单元。 延迟模块比较原点信号分别通过控制单元和参考单元产生的相位或频率差,并产生延迟模块的延迟参数。 信号相位/频率控制模块接收并比较延迟参数以确定绝对时间延迟产生装置的环境PVT条件,以便控制和校正延迟定时发生器从而产生精确的绝对时间延迟。 在各种PVT影响下,绝对时间延迟产生装置能够产生精确的绝对时间信号。

    INTEGRATED CIRCUITS AND METHODS FOR PROVIDING IMPEDANCE OF DRIVER TO DRIVE DATA
    25.
    发明申请
    INTEGRATED CIRCUITS AND METHODS FOR PROVIDING IMPEDANCE OF DRIVER TO DRIVE DATA 有权
    集成电路和驱动器驱动数据阻抗的方法

    公开(公告)号:US20100244891A1

    公开(公告)日:2010-09-30

    申请号:US12723005

    申请日:2010-03-12

    Applicant: Ying-Yu HSU

    Inventor: Ying-Yu HSU

    CPC classification number: H03K19/0005

    Abstract: An integrated circuit includes a pad coupled with a driver. The driver is capable of driving data to the pad. The driver is capable of providing a first set of resistance data substantially fitting to a first curve and a second set of resistance data substantially fitting to a second curve. A portion of at least one of the first set of resistance data and the second set of resistance data is an impedance of the driver to drive data

    Abstract translation: 集成电路包括与驱动器耦合的焊盘。 驾驶员能够将数据驱动到垫子上。 驱动器能够提供基本上适合于第一曲线的第一组电阻数据和基本上适合于第二曲线的第二组电阻数据。 第一组电阻数据和第二组电阻数据中的至少一个的一部分是驱动器驱动数据的阻抗

    REACTOR TO FORM SOLAR CELL ABSORBERS
    26.
    发明申请
    REACTOR TO FORM SOLAR CELL ABSORBERS 审中-公开
    形成太阳能电池吸收器的反应器

    公开(公告)号:US20090183675A1

    公开(公告)日:2009-07-23

    申请号:US12334420

    申请日:2008-12-12

    Abstract: A roll-to-roll or reel-to-reel RTP tool including a reactor having a continuous insert placed in a primary gap of the reactor is provided. The primary gap of the reactor is defined by peripheral reactor walls including a top reactor wall, a bottom reactor wall and side reactor walls. The continuous insert includes a continuous process gap through which a continuous workpiece travels between an entry opening and an exit opening of the insert. An inner space exists between at least one of the insert walls and at least a portion of the peripheral reactor walls that make up the primary gap. At least one gas inlet is connected to the inner space, and at least one exhaust opening connects the process gap as well as the inner space to outside the reactor and carries any gaseous products to outside the process gap and the primary gap of the reactor. Sealable doors or web valves seal the entrance and the exit of the process gap when needed before or after the process, especially when the continuous workpiece stops moving.

    Abstract translation: 提供卷对卷或卷到卷RTP工具,其包括具有放置在反应器的初级间隙中的连续插入物的反应器。 反应器的主要间隙由外围反应器壁限定,包括顶部反应器壁,底部反应器壁和侧壁反应器壁。 连续的插入件包括连续的工件间隙,连续的工件在插入件的进入开口和出口之间行进。 内部空间存在于至少一个插入壁和构成主间隙的外围反应器壁的至少一部分之间。 至少一个气体入口连接到内部空间,并且至少一个排气口将过程间隙以及内部空间连接到反应器外部,并将任何气体产物运送到过程间隙和反应器的初级间隙之外。 密封的门或腹板阀门在工艺之前或之后需要密封过程间隙的入口和出口,特别是当连续工件停止移动时。

    PLIERS HAVING GREATER HOLDING FORCE
    27.
    发明申请
    PLIERS HAVING GREATER HOLDING FORCE 有权
    具有较大保持力的钢笔

    公开(公告)号:US20090133540A1

    公开(公告)日:2009-05-28

    申请号:US11945586

    申请日:2007-11-27

    Applicant: CHIU-YING YU

    Inventor: CHIU-YING YU

    CPC classification number: B25B13/28 B25B13/505

    Abstract: A pair of pliers include a shank, a fixed jaw locked onto the shank, and a movable jaw pivotally mounted on the shank and movable relative to the fixed jaw. Thus, the first contact point of the locking teeth of the fixed jaw and the second contact point of the first engaging teeth of the first toothed face of the movable jaw have a larger friction with a workpiece by a special angle design of the fixed jaw and the movable jaw to enhance the clamping force of the fixed jaw and the movable jaw on the workpiece, so that the workpiece is clamped by the fixed jaw and the movable jaw exactly and closely to prevent the workpiece from being slipped from the fixed jaw and the movable jaw during operation of the pliers.

    Abstract translation: 一对钳子包括柄,锁定在柄上的固定爪,以及枢转地安装在柄上并相对于固定夹爪可移动的可动钳。 因此,固定夹爪的锁定齿的第一接触点和可动夹爪的第一齿面的第一接合齿的第二接触点通过固定夹爪的特殊角度设计与工件具有较大的摩擦力,并且 活动夹爪,增加固定夹爪和工件上的可动夹爪的夹持力,使工件被固定夹爪和可动夹钳精确而紧密地夹紧,防止工件从固定夹爪上滑落, 钳子操作过程中的活动钳口。

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