公开(公告)号：US20100148869A1

公开(公告)日：2010-06-17

申请号：US12617488

申请日：2009-11-12

申请人： Tsuyoshi KAWAKAMI ,  Akihiko Furukawa ,  Satoshi Yamakawa ,  Tetsuya Ilda ,  Masao Kondo ,  Yutaka Hoshino

发明人： Tsuyoshi KAWAKAMI ,  Akihiko Furukawa ,  Satoshi Yamakawa ,  Tetsuya Ilda ,  Masao Kondo ,  Yutaka Hoshino

IPC分类号： H03F3/45

CPC分类号： H03F3/211 ,  H03F1/56 ,  H03F3/26 ,  H03F2200/537 ,  H03F2203/21139

摘要： In order to realize a wider bandwidth of a frequency characteristic of a power amplification circuit, outputs of differential push-pull amplifiers which are matched at respectively different frequencies are combined together by secondary inductors, and the combined signal is outputted.

摘要翻译： 为了实现功率放大电路的频率特性的更宽的带宽，通过二次电感器将分别以不同频率匹配的差分推挽放大器的输出组合在一起，并且输出组合信号。

公开(公告)号：US07479681B2

公开(公告)日：2009-01-20

申请号：US11783779

申请日：2007-04-12

申请人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

发明人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC分类号： H01L23/62

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

摘要翻译： 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US07323735B2

公开(公告)日：2008-01-29

申请号：US11172931

申请日：2005-07-05

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： H01L27/108

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/903 ,  H01L2924/00

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一个存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

公开(公告)号：US07176523B2

公开(公告)日：2007-02-13

申请号：US10921327

申请日：2004-08-19

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

摘要翻译： 在具有漏极偏移区域的高频放大MOSFET中，通过提供用于在源极区域10，漏极区域9和漏电极上引出电极的导体插头13（P 1），尺寸减小并导通电阻降低 连接有第一层布线11a，11d（M1）的层3（4），并且另外，背面的第二层布线12a至12d在导体塞13（P1）上连接到第一层 层布线11s，11d（M 1）。

公开(公告)号：US07087977B2

公开(公告)日：2006-08-08

申请号：US10670258

申请日：2003-09-26

申请人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

发明人： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC分类号： H01L29/00

CPC分类号： H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

摘要： Plural elements forming a high frequency device in one chip are provided by forming a resistor element and the lower electrode of a capacitor element from one identical polycrystal silicon film over a substrate; forming the gate electrode of a power MISFET, upper electrode of the capacitor element, gate electrode of an n-channel type MISFET and gate electrode of a p-channel type MISFET from an identical polycrystal silicon film different from the other polycrystal silicon film and a WSi film; forming a capacitor element having a wiring formed on a silicon oxide film deposited over the substrate as a lower electrode and a wiring formed on the silicon oxide film as the upper electrode in the region MIN; forming a spiral coil in a region IND using an aluminum alloy film identical with that deposited on a silicon oxide film; and forming a bonding pad in a region PAD.

摘要翻译： 通过在基板上形成来自一个相同的多晶硅膜的电容器元件的电阻元件和下电极来提供在一个芯片中形成高频器件的多个元件; 从与其他多晶硅膜不同的相同多晶硅膜形成功率MISFET的栅电极，电容器元件的上电极，n沟道型MISFET的栅电极和p沟道型MISFET的栅电极，以及 WSi电影; 形成电容器元件，其具有形成在沉积在所述基板上的氧化硅膜上的布线作为下电极，以及在所述区域MIN中形成在所述氧化硅膜上的布线作为所述上电极; 使用与沉积在氧化硅膜上的铝合金膜相同的铝合金膜在区域IND中形成螺旋线圈; 以及在区域PAD中形成接合焊盘。

公开(公告)号：US06528848B1

公开(公告)日：2003-03-04

申请号：US09666772

申请日：2000-09-20

申请人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

发明人： Yutaka Hoshino ,  Shuji Ikeda ,  Isao Yoshida ,  Shiro Kamohara ,  Megumi Kawakami ,  Tomoyuki Miyake ,  Masatoshi Morikawa

IPC分类号： H01L2972

CPC分类号： H01L29/66659 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/4827 ,  H01L23/53219 ,  H01L23/53295 ,  H01L27/0255 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/1045 ,  H01L29/105 ,  H01L29/1083 ,  H01L29/4175 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/4916 ,  H01L29/7835 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： In a high frequency amplifying MOSFET having a drain offset region, the size is reduced and the on-resistance is decreased by providing conductor plugs 13 (P1) for leading out electrodes on a source region 10, a drain region 9 and leach-through layers 3 (4), to which a first layer wirings 11a, 11d (M1) are connected and, further, backing second layer wirings 12a to 12d are connected on the conductor plugs 13 (P1) to the first layer wirings 11s, 11d (M1).

公开(公告)号：US5780910A

公开(公告)日：1998-07-14

申请号：US682243

申请日：1996-07-17

申请人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

发明人： Naotaka Hashimoto ,  Yutaka Hoshino ,  Shuji Ikeda

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L23/522 ,  H01L27/10 ,  H01L27/11 ,  G11C7/00 ,  G11C11/00 ,  H01L23/62

CPC分类号： H01L27/11 ,  G11C11/4125 ,  H01L23/5222 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/0207 ,  H01L2924/0002 ,  Y10S257/903

摘要： In a complete CMOS SRAM having a memory cell composed of six MISFETs formed over a substrate, a capacitor element having a stack structure is formed of a lower electrode covering the memory cell, an upper electrode, and a capacitor insulating film (dielectric film) interposed between the lower electrode and the upper electrode. One electrode (the lower electrode) of the capacitor element is connected to one storage node of a flip-flop circuit, and the other electrode (the upper electrode) is connected to the other storage node. As a result, the storage node capacitance of the memory cell of the SRAM is increased to improve the soft error resistance.

摘要翻译： 在具有由衬底上形成的六个MISFET构成的存储单元的完整CMOS SRAM中，具有堆叠结构的电容器元件由覆盖存储单元的下电极，上电极和插入了电容器绝缘膜（电介质膜）的电极形成 在下电极和上电极之间。 电容器元件的一个电极（下电极）连接到触发器电路的一个存储节点，另一个电极（上电极）连接到另一存储节点。 结果，SRAM的存储单元的存储节点电容增加，以提高软错误电阻。

公开(公告)号：US5208364A

公开(公告)日：1993-05-04

申请号：US904412

申请日：1992-06-25

申请人： Hiroaki Ohkuma ,  Yutaka Hoshino ,  Yosuke Sawada ,  Derek Hook

发明人： Hiroaki Ohkuma ,  Yutaka Hoshino ,  Yosuke Sawada ,  Derek Hook

IPC分类号： C07C229/64

CPC分类号： C07C229/64

摘要： Novel compounds derived from cultures of Streptomyces sp. AA2807 are useful as 5-lipoxygenase inhibitors.

摘要翻译： 衍生自Streptomyces sp。 AA2807可用作5-脂氧合酶抑制剂。

公开(公告)号：US08842955B2

公开(公告)日：2014-09-23

申请号：US13142163

申请日：2009-12-24

申请人： Masayoshi Tsukamoto ,  Yutaka Hoshino ,  Noboru Okada

发明人： Masayoshi Tsukamoto ,  Yutaka Hoshino ,  Noboru Okada

IPC分类号： G02B6/44

CPC分类号： G02B6/4402 ,  G02B6/4433

摘要： An optical fiber cable enabling further reduction of possibilities of disconnection of optical fiber due to, for instance, cicada oviposition. The optical fiber cable (10) is provided with: an optical fiber core (1); a tension member (2), which is arranged in parallel to the optical fiber core (1) on one side or on the both sides of the optical fiber core (1); and a sheath (3) which integrally covers the optical fiber core (1) and the tension member (2). At least one portion of the sheath (3) is composed of a polymeric material having a yield point stress of 12 MPa or higher.

摘要翻译： 一种光纤电缆，能够进一步降低由于例如蝉产卵而导致的光纤断开的可能性。 光缆（10）设有：光纤芯（1）; 张力构件（2），其在所述光纤芯（1）的一侧或两侧平行于所述光纤芯（1）布置; 以及一体地覆盖光纤芯（1）和张紧构件（2）的护套（3）。 护套（3）的至少一部分由屈服点应力为12MPa以上的聚合物材料构成。

公开(公告)号：US08344454B2

公开(公告)日：2013-01-01

申请号：US13048926

申请日：2011-03-16

申请人： Kyoya Nitta ,  Yutaka Hoshino

发明人： Kyoya Nitta ,  Yutaka Hoshino

IPC分类号： H01L27/12

CPC分类号： H01L29/42384 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/4908 ,  H01L29/78612 ,  H01L29/78654 ,  H01L2924/0002 ,  H01L2924/00

摘要： An object of the invention is to provide a semiconductor device having improved performance, high reliability, and a reduced chip size, in particular, to provide a semiconductor device having an MOSFET over an SOI substrate capable of maintaining its reliability while controlling the potential of a well below a gate electrode and preventing generation of parasitic capacitance. Generation of parasitic capacitance is prevented by controlling the potential of a well below a gate electrode by using a well contact plug passing through a hole portion formed in a gate electrode wiring. Generation of defects in a gate insulating film is prevented by making use of a gettering effect produced by causing an element isolation region to extend along the gate electrode.

摘要翻译： 本发明的目的是提供一种具有改进的性能，高可靠性和减小的芯片尺寸的半导体器件，特别是提供一种在SOI衬底上具有MOSFET的半导体器件，其能够保持其可靠性，同时控制一个 远低于栅电极并防止寄生电容的产生。 通过使用穿过形成在栅电极布线中的孔部的阱接触塞来控制阱下方的阱的电位来防止寄生电容的产生。 通过利用通过使元件隔离区域沿着栅电极延伸而产生的吸杂效应来防止栅绝缘膜中的缺陷的产生。