公开(公告)号：US20090167803A1

公开(公告)日：2009-07-02

申请号：US12323296

申请日：2008-11-25

Applicant: Tetsuo Uchiyama ,  Hisashi Ishikawa

Inventor： Tetsuo Uchiyama ,  Hisashi Ishikawa

IPC: B41J2/205

CPC classification number: B41J2/2052

Abstract: An image forming apparatus which forms a halftone image on a print medium by using a multipass process to scan a printhead N (N is an integer of 2 or more) times in a single area on the print medium and form dots by each scan operation includes a pass division unit which sets the print density of a scan operation in the first pass so as to prevent dots from overlapping with each other on the print medium, and sets the print densities of scan operations in the second to Nth passes, a tone reduction unit which generates print data of the respective scan operations in accordance with the print densities set by the pass division unit, and a printhead which prints a halftone image on a print medium on the basis of the print data generated by the tone reduction unit.

Abstract translation: 一种图像形成装置，其通过使用多次处理在打印介质上在打印介质上的单个区域中扫描打印头N（N为2以上的整数）次而在打印介质上形成半色调图像，并且通过每次扫描操作形成点， 通过分割单元，其在第一遍中设置扫描操作的打印浓度，以防止点在打印介质上彼此重叠，并且将扫描操作的打印浓度设置在第二到第N遍，色调降低 根据由通过分割单元设置的打印浓度生成各扫描操作的打印数据的打印单元，以及基于由色调降低单元产生的打印数据在打印介质上打印半色调图像的打印头。

公开(公告)号：US20070194407A1

公开(公告)日：2007-08-23

申请号：US11783779

申请日：2007-04-12

Applicant: Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

Inventor： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC: H01L29/00

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Abstract translation: 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US07167420B2

公开(公告)日：2007-01-23

申请号：US10499450

申请日：2002-12-20

Applicant: Morinobu Endo ,  Tetsuo Uchiyama ,  Akio Yamaguchi ,  Yasuo Kondo ,  Hiroshi Aoyama ,  Koichiro Jujo ,  Kazutoshi Takeda ,  Masato Takenaka ,  Shigeo Suzuki ,  Takeshi Tokoro

Inventor： Morinobu Endo ,  Tetsuo Uchiyama ,  Akio Yamaguchi ,  Yasuo Kondo ,  Hiroshi Aoyama ,  Koichiro Jujo ,  Kazutoshi Takeda ,  Masato Takenaka ,  Shigeo Suzuki ,  Takeshi Tokoro

IPC: G04F5/00 ,  G04B29/00 ,  F03G1/00 ,  B32B9/00 ,  C08K3/00

CPC classification number: G04C3/008 ,  G04B13/021 ,  Y10S977/724 ,  Y10S977/734 ,  Y10T428/2918 ,  Y10T428/30

Abstract: The invention relates to a timepiece which has a resin substrate, rotors, and wheel trains, and relates to a wheel train apparatus which has a resin substrate, bearing members, gear wheel, and the like. The invention is constituted by a timepiece comprising; a gear wheel, and a substrate which supports a shaft of a rotor and/or a shaft of the gear wheel, the substrate being formed from a filled resin. Alternatively the invention is constituted by a wheel train apparatus comprising: a gear wheel; a substrate which supports one shaft section of the gear wheel, and a bridge which rotatably supports an other shaft section of the gear wheel, the substrate and the bridge being formed from a filled resin.

Abstract translation: 本发明涉及具有树脂基板，转子和轮列的钟表，涉及具有树脂基板，轴承部件，齿轮等的轮系装置。 本发明由钟表构成，包括： 齿轮和支撑转子的轴和/或齿轮的轴的基板，所述基板由填充的树脂形成。 或者，本发明由轮系装置构成，包括：齿轮; 支撑齿轮的一个轴部的基板和可旋转地支撑齿轮的另一个轴部的桥，基板和桥由填充的树脂形成。

公开(公告)号：US20060164925A1

公开(公告)日：2006-07-27

申请号：US10499450

申请日：2002-12-20

Applicant: Morinobu Endo ,  Tetsuo Uchiyama ,  Akio Yamaguchi ,  Yasuo Kondo ,  Hiroshi Aoyama ,  Koichiro Jujo ,  Kazutoshi Takeda ,  Masato Takenaka ,  Shigeo Suzuki ,  Takeshi Tokoro

Inventor： Morinobu Endo ,  Tetsuo Uchiyama ,  Akio Yamaguchi ,  Yasuo Kondo ,  Hiroshi Aoyama ,  Koichiro Jujo ,  Kazutoshi Takeda ,  Masato Takenaka ,  Shigeo Suzuki ,  Takeshi Tokoro

IPC: G04B29/00

CPC classification number: G04C3/008 ,  G04B13/021 ,  Y10S977/724 ,  Y10S977/734 ,  Y10T428/2918 ,  Y10T428/30

Abstract: The invention relates to a timepiece which has a resin substrate, rotors, and wheel trains, and relates to a wheel train apparatus which has a resin substrate, bearing members, gear wheel, and the like. The invention is constituted by a timepiece comprising; a gear wheel, and a substrate which supports a shaft of a rotor and/or a shaft of the gear wheel, the substrate being formed from a filled resin. Alternatively the invention is constituted by a wheel train apparatus comprising: a gear wheel; a substrate which supports one shaft section of the gear wheel, and a bridge which rotatably supports an other shaft section of the gear wheel, the substrate and the bridge being formed from a filled resin.

Abstract translation: 本发明涉及一种具有树脂基板，转子和轮列的钟表，涉及具有树脂基板，轴承部件，齿轮等的轮系装置。 本发明由钟表构成，包括： 齿轮和支撑转子的轴和/或齿轮的轴的基板，所述基板由填充的树脂形成。 或者，本发明由轮系装置构成，包括：齿轮; 支撑齿轮的一个轴部的基板和可旋转地支撑齿轮的另一个轴部的桥，基板和桥由填充的树脂形成。

公开(公告)号：US4837435A

公开(公告)日：1989-06-06

申请号：US210810

申请日：1988-06-24

Applicant: Toshihiko Sakuhara ,  Fumiki Sakai ,  Tetsuo Uchiyama

Inventor： Toshihiko Sakuhara ,  Fumiki Sakai ,  Tetsuo Uchiyama

IPC: G01N23/00 ,  G01B7/34 ,  G01N27/00 ,  G01N37/00 ,  G01Q10/06 ,  G01Q30/04 ,  G01Q60/10 ,  G01Q60/40 ,  H01J37/26 ,  H01J37/28

CPC classification number: G01Q60/16 ,  B82Y35/00 ,  G01Q10/02 ,  G01Q10/04 ,  G01Q10/06 ,  G01Q30/04 ,  Y10S977/861 ,  Y10S977/868

Abstract: The tunneling scanning microscope which is provided with a light source to irradiate a sample with light, particularly with light having one wavelength. The apparatus is used for the investigation of the surface structure of materials which have very low conductivity but increase their conductivities under light irradiation. In particular, the apparatus selectively provides an atomic image of an element of a compound in response to a selected wavelength.

公开(公告)号：US08080831B2

公开(公告)日：2011-12-20

申请号：US12784560

申请日：2010-05-21

Applicant: Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

Inventor： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC: H01L21/02

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Abstract translation: 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US20100097157A1

公开(公告)日：2010-04-22

申请号：US12644971

申请日：2009-12-22

Applicant: Fumitaka NAKAYAMA ,  Masatoshi MORIKAWA ,  Yutaka HOSHINO ,  Tetsuo UCHIYAMA

Inventor： Fumitaka NAKAYAMA ,  Masatoshi MORIKAWA ,  Yutaka HOSHINO ,  Tetsuo UCHIYAMA

IPC: H03H7/38 ,  H01L27/06 ,  H03H2/00

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Abstract translation: 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US20090108371A1

公开(公告)日：2009-04-30

申请号：US12341330

申请日：2008-12-22

Applicant: Fumitaka NAKAYAMA ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

Inventor： Fumitaka NAKAYAMA ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC: H01L27/06 ,  H01L29/86

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

Abstract: A semiconductor device including a MISFET formed in a well at a main surface of a substrate, a second MISFET formed at a main surface of the substrate, and a passive element formed over the main surface of the substrate and having two terminals. A conductive film is formed at a rear face of the semiconductor substrate. The conductive film is connected with a fixed potential and also electrically connected with the conductive film.

Abstract translation: 一种半导体器件，包括形成在基板的主表面的阱中的MISFET，形成在基板的主表面处的第二MISFET以及形成在基板的主表面上并具有两个端子的无源元件。 导电膜形成在半导体衬底的背面。 导电膜与固定电位连接，并与导电膜电连接。

公开(公告)号：US07306879B2

公开(公告)日：2007-12-11

申请号：US10445742

申请日：2003-05-27

Applicant: Yasushi Inda ,  Kazuo Ohara ,  Tetsuo Uchiyama ,  Morinobu Endo

Inventor： Yasushi Inda ,  Kazuo Ohara ,  Tetsuo Uchiyama ,  Morinobu Endo

IPC: H01M4/62

CPC classification number: H01M10/052 ,  H01M2/162 ,  H01M10/0562

Abstract: A lithium ion secondary cell comprises a positive electrode, a negative electrode, a solid electrolyte and a fiber layer provided in an interface between the solid electrolyte and the positive electrode and/or in an interface between the solid electrolyte and the negative electrode.

公开(公告)号：US20060261442A1

公开(公告)日：2006-11-23

申请号：US11493829

申请日：2006-07-27

Applicant: Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

Inventor： Fumitaka Nakayama ,  Masatoshi Morikawa ,  Yutaka Hoshino ,  Tetsuo Uchiyama

IPC: H01L29/00

CPC classification number: H01L21/823814 ,  H01L21/26586 ,  H01L23/3677 ,  H01L23/5223 ,  H01L23/5227 ,  H01L27/0617 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/0922 ,  H01L28/20 ,  H01L28/40 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/4238 ,  H01L29/456 ,  H01L29/4975 ,  H01L29/66659 ,  H01L2224/48227 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2924/13091 ,  H01L2924/30107 ,  H03F3/193 ,  H01L2924/00

Abstract: A semiconductor device includes a transmission power amplifier having cascaded MOSFET amplification stages disposed over a main surface of a semiconductor substrate. A CMOSFET control circuit controls the amplification stages. A first capacitor is also provided having upper and lower metal film electrodes formed over the main surface of the semiconductor substrate. The amplification stages are electrically coupled to one another via an inter-stage matching circuit which includes the first capacitor.

Abstract translation: 半导体器件包括具有设置在半导体衬底的主表面上的级联MOSFET放大级的发射功率放大器。 CMOSFET控制电路控制放大级。 还提供了第一电容器，其具有形成在半导体衬底的主表面上的上金属膜电极和下金属膜电极。 放大级通过包括第一电容器的级间匹配电路彼此电耦合。