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公开(公告)号：US20180032447A1
公开(公告)日：2018-02-01
申请号：US15417632
申请日：2017-01-27
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Kaplan , Jeremy W. Powell , Thomas R. Woller
IPC: G06F12/14 , G06F12/1009
CPC classification number: G06F12/1425 , G06F9/45558 , G06F9/52 , G06F12/1009 , G06F12/1483 , G06F2009/45583 , G06F2009/45587 , G06F2212/1052 , G06F2212/151 , G06F2212/65 , G06F2212/651
Abstract: A table walker receives, from a requesting entity, a request to translate a first address into a second address associated with a page of memory. During a corresponding table walk, when a lock indicator in an entry in a reverse map table (RMT) for the page is set to mark the entry in the RMT as locked, the table walker halts processing the request and performs a remedial action. In addition, when the request is associated with a write access of the page and an immutable indicator in the entry in the RMT is set to mark the page as immutable, the table walker halts processing the request and performs the remedial action. Otherwise, when the entry in the RMT is not locked and the page is not marked as immutable for a write access, the table walker continues processing the request.
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公开(公告)号：US20180032443A1
公开(公告)日：2018-02-01
申请号：US15224302
申请日：2016-07-29
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Kaplan , Jeremy W. Powell , Thomas R. Woller
IPC: G06F12/1027 , G06F9/455 , G06F12/1009
CPC classification number: G06F12/1027 , G06F9/45558 , G06F12/1009 , G06F2009/45583 , G06F2212/657 , G06F2212/68
Abstract: The described embodiments perform a method for handling memory accesses by virtual machines in a computing device. The described embodiments include a reverse map table (RMT) and a separate guest accessed pages table (GAPT) for each virtual machine. The RMT has a plurality of entries, each entry including information for identifying a virtual machine that is permitted to access an associated page of data in a memory. Each GAPT has a record of pages being accessed by a corresponding virtual machine. During operation, a table walker receives a request from a given virtual machine to translate a guest physical address to a system physical address. The table walker checks at least one of the RMT and a corresponding GAPT to determine whether the given virtual machine has access to a corresponding page. If not, the table walker terminates the translating. Otherwise, the table walker completes the translating.
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公开(公告)号：US09792448B2
公开(公告)日：2017-10-17
申请号：US14494643
申请日：2014-09-24
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Kaplan , Thomas Roy Woller , Ronald Perez
CPC classification number: G06F21/602 , G06F9/45558 , G06F12/1036 , G06F12/1408 , G06F21/53 , G06F2009/4557 , G06F2009/45583 , G06F2009/45587 , G06F2212/402
Abstract: A processor employs a hardware encryption module in the processor's memory access path to cryptographically isolate secure information. In some embodiments, the encryption module is located at a memory controller (e.g. northbridge) of the processor, and each memory access provided to the memory controller indicates whether the access is a secure memory access, indicating the data associated with the memory access is designated for cryptographic protection, or a non-secure memory access. For secure memory accesses, the encryption module performs encryption (for write accesses) or decryption (for read accesses) of the data associated with the memory access.
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公开(公告)号：US09189417B2
公开(公告)日：2015-11-17
申请号：US13672188
申请日：2012-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Kaplan , Stephen P. Thompson
IPC: G06F12/10
CPC classification number: G06F12/1027 , G06F12/10 , G06F12/1009
Abstract: A method includes performing a speculative tablewalk. The method includes performing a tablewalk to determine an address translation for a speculative operation and determining whether the speculative operation has been upgraded to a non-speculative operation concurrently with performing the tablewalk. An apparatus is provided that includes a load-store unit to maintain execution operations. The load-store unit includes a tablewalker to perform a tablewalk and includes an input indicative of the operation being speculative or non-speculative as well as a state machine to determine actions performed during the tablewalk based on the input. The apparatus also includes a translation look-aside buffer. Computer readable storage devices for performing the methods and adapting a fabrication facility to manufacture the apparatus are provided.
Abstract translation: 一种方法包括执行推测性行进。 该方法包括执行行进台以确定用于投机操作的地址转换，并且确定投机操作是否已经与执行台式机同时升级到非投机操作。 提供一种装置，其包括用于维持执行操作的加载存储单元。 加载存储单元包括执行台面的行进者，并且包括指示操作是投机或不推测的输入以及基于输入来确定在行进过程中执行的动作的状态机。 该装置还包括翻译后备缓冲器。 提供了用于执行方法和适配制造设备以制造该装置的计算机可读存储装置。
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公开(公告)号：US08997210B1
公开(公告)日：2015-03-31
申请号：US14052182
申请日：2013-10-11
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： David A. Kaplan , Philip Ng
CPC classification number: G06F9/4411 , G06F9/30145 , G06F9/3881
Abstract: A method includes executing microcode in a processing unit of a processor to implement a machine instruction, wherein the microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction. A processor includes a public communication bus, a peripheral device coupled to the public communication bus, and a processing unit. The processing unit is to execute microcode to implement a machine instruction. The microcode is to manipulate the processing unit to access a peripheral device on a public communication bus at a private address not visible to other devices on the public communication bus and not specified in the machine instruction.
Abstract translation: 一种方法包括在处理器的处理单元中执行微代码以实现机器指令，其中微代码是操纵处理单元以公共通信总线上的外部设备访问公用通信上的其他设备不可见的专用地址 总线，并未在机器指令中指定。 处理器包括公共通信总线，耦合到公共通信总线的外围设备和处理单元。 处理单元是执行微代码来实现机器指令。 微代码是操纵处理单元以公用通信总线上的公共通信总线上的外部设备访问公共通信总线上的其他设备不可见的私有地址，并且未在机器指令中指定。
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Patent Agency Ranking
公开(公告)号：US20140310500A1
公开(公告)日：2014-10-16
申请号：US13861267
申请日：2013-04-11
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： David A. Kaplan , Jeff Rupley
IPC: G06F12/10
CPC classification number: G06F12/1009 , G06F9/30043 , G06F9/3824
Abstract: The present application describes embodiments of a method and apparatus including a page cross misalign buffer. Some embodiments of the apparatus include a store queue for a plurality of entries configured to store information associated with store instructions. A respective entry in the store queue can store a first portion of information associated with a page crossing store instruction. Some embodiments of the apparatus also include one or more buffers configured to store a second portion of information associated with the page crossing store instruction.
Abstract translation: 本申请描述了包括页面交叉对准缓冲器的方法和装置的实施例。 该装置的一些实施例包括用于多个条目的存储队列，其被配置为存储与存储指令相关联的信息。 存储队列中的相应条目可以存储与页面交叉存储指令相关联的信息的第一部分。 该装置的一些实施例还包括配置成存储与页面交叉存储指令相关联的信息的第二部分的一个或多个缓冲器。
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公开(公告)号：US20140129776A1
公开(公告)日：2014-05-08
申请号：US13667095
申请日：2012-11-02
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： David A. Kaplan , Jeff Rupley , Tarun Nakra
IPC: G06F12/08
CPC classification number: G06F9/30065 , G06F9/30043 , G06F9/3861 , G06F12/0802 , G06F12/0815
Abstract: A method is provided for executing a cacheable store. The method includes determining whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. The store instruction is replayed in response to determining to replay the store instruction. An apparatus is provided that includes a store queue (SQ) configurable to determine whether to replay a store instruction to re-acquire one or more cache lines based upon a state of the cache line(s) and an execution phase of the store instruction. Computer readable storage devices for adapting a fabrication facility to manufacture the apparatus are provided.
Abstract translation: 提供了一种用于执行可缓存存储的方法。 该方法包括基于高速缓存行的状态和存储指令的执行阶段确定是否重放存储指令以重新获取一个或多个高速缓存行。 响应于确定重播商店指令而重放存储指令。 提供了一种装置，其包括可配置以基于高速缓存行的状态和存储指令的执行阶段来确定是否重播存储指令以重新获取一个或多个高速缓存行的存储队列（SQ）。 提供了用于使制造设备适应制造装置的计算机可读存储装置。
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公开(公告)号：US20250130958A1
公开(公告)日：2025-04-24
申请号：US18926087
申请日：2024-10-24
Applicant: Advanced Micro Devices, Inc.
Inventor： Reshma Lal , David A. Kaplan , Jelena Ilic
IPC: G06F12/14 , G06F12/1009
Abstract: Root-trusted guest memory page management is described. A root-trusted guest is loaded by a hardware platform and authenticated. The root-trusted guest is configured to manage memory operations of different guests via special privileges that permit the root-trusted guest to execute memory operations using a guest's private memory page. To do so, a guest page table includes a novel “T-bit” in each entry, which indicates whether the root-trusted guest or a different guest owns the associated memory page. Each entry in the guest page table for the root-trusted guest additionally includes a “C-bit” that indicates whether the corresponding memory page is a protected page. Combined C-bit and T-bit values for a page table entry dictate whether operations performed as part of handling a guest's memory request are offloaded from the hardware platform to the root-trusted guest.
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公开(公告)号：US20200034144A1
公开(公告)日：2020-01-30
申请号：US16046949
申请日：2018-07-26
Applicant: Advanced Micro Devices, Inc.
Inventor： Marius Evers , David A. Kaplan , Debjit Das Sarma
Abstract: Overhead associated with verifying function return addresses to protect against security exploits is reduced by taking advantage of branch prediction mechanisms for predicting return addresses. More specifically, returning from a function includes popping a return address from a data stack. Well-known security exploits overwrite the return address on the data stack to hijack control flow. In some processors, a separate data structure referred to as a control stack is used to verify the data stack. When a return instruction is executed, the processor issues an exception if the return addresses on the control stack and the data stack are not identical. This overhead can be avoided by taking advantage of the return address stack, which is a data structure used by the branch predictor to predict return addresses. In most situations, if this prediction is correct, the above check does not need to occur, thus reducing the associated overhead.
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公开(公告)号：US10169244B2
公开(公告)日：2019-01-01
申请号：US15224302
申请日：2016-07-29
Applicant: Advanced Micro Devices, Inc.
Inventor： David A. Kaplan , Jeremy W. Powell , Thomas R. Woller
IPC: G06F12/10 , G06F12/1027 , G06F12/1009 , G06F9/455
Abstract: The described embodiments perform a method for handling memory accesses by virtual machines in a computing device. The described embodiments include a reverse map table (RMT) and a separate guest accessed pages table (GAPT) for each virtual machine. The RMT has a plurality of entries, each entry including information for identifying a virtual machine that is permitted to access an associated page of data in a memory. Each GAPT has a record of pages being accessed by a corresponding virtual machine. During operation, a table walker receives a request from a given virtual machine to translate a guest physical address to a system physical address. The table walker checks at least one of the RMT and a corresponding GAPT to determine whether the given virtual machine has access to a corresponding page. If not, the table walker terminates the translating. Otherwise, the table walker completes the translating.
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