公开(公告)号：US20210200649A1

公开(公告)日：2021-07-01

申请号：US16729994

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F11/14 ,  G06F3/06

Abstract: A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.

公开(公告)号：US20210200467A1

公开(公告)日：2021-07-01

申请号：US16730070

申请日：2019-12-30

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan

IPC: G06F3/06

Abstract: A memory controller interfaces with a non-volatile storage class memory (SCM) module over a heterogenous memory channel, and includes a command queue for receiving memory access commands. A memory interface queue is coupled to the command queue for holding outgoing commands. A non-volatile command queue is coupled to the command queue for storing non-volatile read commands that are placed in the memory interface queue. An arbiter selects entries from the command queue, and places them in the memory interface queue for transmission over a heterogenous memory channel. A control circuit is coupled to the heterogenous memory channel for receiving a ready response from the non-volatile SCM module indicating that responsive data is available for a non-volatile read command, and in response to receiving the ready response, causing a send command to be placed in the memory interface queue for commanding the non-volatile SCM module to send the responsive data.

公开(公告)号：US20210049062A1

公开(公告)日：2021-02-18

申请号：US16705913

申请日：2019-12-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James R. Magro ,  Kevin Michael Lepak ,  Vilas Sridharan

IPC: G06F11/07 ,  G06F11/10 ,  H03M13/29

Abstract: A data processing system includes a memory channel, a memory coupled to the memory channel, and a data processor. The data processor is coupled to the memory channel and accesses the memory over the memory channel using a packet structure defining a plurality of commands and having corresponding address bits, data bits, and user bits. The data processor communicates with the memory over the memory channel using a first type of error code. In response to a write access request, the data processor calculates a different, second type of error code and appends each bit of the second type of error code as a corresponding one of the user bits. The memory stores the user bits in the memory in response to a write command, and transfers the user bits to the data processor in a read response packet in response to a read command.

公开(公告)号：US10684969B2

公开(公告)日：2020-06-16

申请号：US15211815

申请日：2016-07-15

Applicant: Advanced Micro Devices, Inc.

Inventor： James R. Magro ,  Kedarnath Balakrishnan ,  Jackson Peng ,  Hideki Kanayama

IPC: G06F13/16 ,  G06F13/40

Abstract: In one form, a memory controller includes a command queue and an arbiter. The command queue receives and stores memory access requests. The arbiter includes a plurality of sub-arbiters for providing a corresponding plurality of sub-arbitration winners from among the memory access requests during a controller cycle, and for selecting among the plurality of sub-arbitration winners to provide a plurality of memory commands in a corresponding controller cycle. In another form, a data processing system includes a memory accessing agent for providing memory accesses requests, a memory system, and the memory controller coupled to the memory accessing agent and the memory system.

公开(公告)号：US20190196995A1

公开(公告)日：2019-06-27

申请号：US15850751

申请日：2017-12-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Guanhao Shen ,  Ravindra N. Bhargava ,  Kedarnath Balakrishnan

IPC: G06F13/30 ,  G06F13/16 ,  G06F3/06

CPC classification number: G06F13/30 ,  G06F3/0659 ,  G06F3/0673 ,  G06F13/1626 ,  G06F13/1642

Abstract: Systems, apparatuses, and methods for performing efficient memory accesses for a computing system are disclosed. When a memory controller in a computing system determines a threshold number of memory access requests have not been sent to the memory device in a current mode of a read mode and a write mode, a first cost corresponding to a latency associated with sending remaining requests in either the read queue or the write queue associated with the current mode is determined. If the first cost exceeds the cost of a data bus turnaround, the cost of a data bus turnaround comprising a latency incurred when switching a transmission direction of the data bus from one direction to an opposite direction, then a second cost is determined for sending remaining memory access requests to the memory device. If the second cost does not exceed the cost of the data bus turnaround, then a time for the data bus turnaround is indicated and the current mode of the memory controller is changed.

公开(公告)号：US10296230B1

公开(公告)日：2019-05-21

申请号：US15853090

申请日：2017-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G06F12/00 ,  G06F3/06 ,  G11C7/22 ,  G06F13/16

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

公开(公告)号：US20170345482A1

公开(公告)日：2017-11-30

申请号：US15408126

申请日：2017-01-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan

IPC: G11C11/406 ,  G06F3/06

CPC classification number: G11C11/40611 ,  G06F3/0611 ,  G06F3/0634 ,  G06F3/0679 ,  G11C11/40603 ,  G11C11/40615

Abstract: A data processing system includes a memory channel and a data processor coupled to the memory channel. The data processor is adapted to access at least one rank and has refresh logic. In response to an activation of the refresh logic, the data processor generates refresh cycles to a bank of the memory channel. The data processor selects one of a first state corresponding to a first auto-refresh command that causes the data processor to auto-refresh the bank, and a second state corresponding to a second auto-refresh command that causes the data processor to auto-refresh a selected subset of the bank. The data processor initiates a switch between the first state and the second state in response to the refresh logic detecting a first condition related to the bank, and between the second state and the first state in response to the refresh logic circuit detecting a second condition.

公开(公告)号：US12243576B2

公开(公告)日：2025-03-04

申请号：US18198709

申请日：2023-05-17

Applicant: Advanced Micro Devices, Inc.

Inventor： Jing Wang ,  Kedarnath Balakrishnan ,  Kevin M. Brandl ,  James R. Magro

IPC: G06F9/24 ,  G06F1/3203 ,  G06F9/4401 ,  G11C11/406

Abstract: A method for performing stutter of dynamic random access memory (DRAM) where a system on a chip (SOC) initiates bursts of requests to the DRAM to fill buffers to allow the DRAM to self-refresh is disclosed. The method includes issuing, by a system management unit (SMU), a ForceZQCal command to the memory controller to initiate the stutter procedure in response to receiving a timeout request, such as an SMU ZQCal timeout request, periodically issuing a power platform threshold (PPT) request, by the SMU, to the memory controller, and sending a ForceZQCal command prior to a PPT request to ensure re-training occurs after ZQ Calibration. The ForceZQCal command issued prior to PPT request may reduce the latency of the stutter. The method may further include issuing a ForceZQCal command prior to each periodic re-training.

公开(公告)号：US12204754B2

公开(公告)日：2025-01-21

申请号：US16959503

申请日：2018-09-20

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  James Raymond Magro

IPC: G06F3/06 ,  G06F13/16 ,  G11C7/22

Abstract: Systems, apparatuses, and methods for performing scheduling memory requests for issue to two different memory types are disclosed. A computing system includes one or more clients for processing applications. A heterogeneous memory channel within a memory controller transfers memory traffic between the memory controller and a memory bus connected to each of a first memory and a second memory different from the first memory. The memory controller determines a next given point in time that does not already have read response data scheduled to be driven on the memory bus. The memory controller determines whether there is time to schedule a first memory access command for accessing the first memory and a second memory access command for accessing the second memory. If there is sufficient time for each, then one of the access commands is selected based on weighted criteria.

公开(公告)号：US20240211173A1

公开(公告)日：2024-06-27

申请号：US18086942

申请日：2022-12-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Kedarnath Balakrishnan ,  Jing Wang ,  Guanhao Shen

IPC: G06F3/06

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673

Abstract: A memory controller includes an arbiter. The arbiter is configured to elevate a priority of memory access requests that generate row activate commands in response to receiving a same-bank refresh request, and to send a same-bank refresh command in response to receiving the same-bank refresh request.