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公开(公告)号：US11500778B2
公开(公告)日：2022-11-15
申请号：US16813075
申请日：2020-03-09
Applicant: Advanced Micro Devices, Inc.
Inventor： Nuwan S. Jayasena , James Michael O'Connor , Michael Mantor
IPC: G06F12/0862 , G06F9/52 , G06F8/41
Abstract: Embodiments include methods, systems and non-transitory computer-readable computer readable media including instructions for executing a prefetch kernel with reduced intermediate state storage resource requirements. These include executing a prefetch kernel on a graphics processing unit (GPU), such that the prefetch kernel begins executing before a processing kernel. The prefetch kernel performs memory operations that are based upon at least a subset of memory operations in the processing kernel.
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公开(公告)号：US11295507B2
公开(公告)日：2022-04-05
申请号：US17091957
申请日：2020-11-06
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mark Leather , Michael Mantor
Abstract: A graphics processing unit (GPU) or other apparatus includes a plurality of shader engines. The apparatus also includes a first front end (FE) circuit and one or more second FE circuits. The first FE circuit is configured to schedule geometry workloads for the plurality of shader engines in a first mode. The first FE circuit is configured to schedule geometry workloads for a first subset of the plurality of shader engines and the one or more second FE circuits are configured to schedule geometry workloads for a second subset of the plurality of shader engines in a second mode. In some cases, a partition switch is configured to selectively connect the first FE circuit or the one or more second FE circuits to the second subset of the plurality of shader engines depending on whether the apparatus is in the first mode or the second mode.
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公开(公告)号：US11263044B2
公开(公告)日：2022-03-01
申请号：US16692856
申请日：2019-11-22
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Mangesh P. Nijasure , Michael Mantor , Ashkan Hosseinzadeh Namin , Louis Regniere
Abstract: A graphics processing unit (GPU) adjusts a frequency of clock based on identifying a program thread executing at the processing unit, wherein the program thread is detected based on a workload to be executed. By adjusting the clock frequency based on the identified program thread, the processing unit adapts to different processing demands of different program threads. Further, by identifying the program thread based on workload, the processing unit adapts the clock frequency based on processing demands, thereby conserving processing resources.
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公开(公告)号：US10546365B2
公开(公告)日：2020-01-28
申请号：US15843968
申请日：2017-12-15
Applicant: ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
Inventor： Michael Mantor , Laurent Lefebvre , Mika Tuomi , Kiia Kallio
Abstract: An apparatus, such as a head mounted device (HMD), includes one or more processors configured to implement a graphics pipeline that renders pixels in window space with a nonuniform pixel spacing. The apparatus also includes a first distortion function that maps the non-uniformly spaced pixels in window space to uniformly spaced pixels in raster space. The apparatus further includes a scan converter configured to sample the pixels in window space through the first distortion function. The scan converter is configured to render display pixels used to generate an image for display to a user based on the uniformly spaced pixels in raster space. In some cases, the pixels in the window space are rendered such that a pixel density per subtended area is constant across the user's field of view.
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公开(公告)号：US10360177B2
公开(公告)日：2019-07-23
申请号：US15189054
申请日：2016-06-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Syed Zohaib M. Gilani , Jiasheng Chen , QingCheng Wang , YunXiao Zou , Michael Mantor , Bin He , Timour T. Paltashev
IPC: G06F15/80 , G06F1/3234 , G06T15/00
Abstract: Described is a method and processing apparatus to improve power efficiency by gating redundant threads processing. In particular, the method for gating redundant threads in a graphics processor includes determining if data for a thread and data for at least another thread are within a predetermined similarity threshold, gating execution of the at least another thread if the data for the thread and the data for the at least another thread are within the predetermined similarity threshold, and using an output data from the thread as an output data for the at least another thread.
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Patent Agency Ranking
公开(公告)号：US20190122417A1
公开(公告)日：2019-04-25
申请号：US16179376
申请日：2018-11-02
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Michael Mantor , Laurent Lefebvre , Mark Fowler , Timothy Kelley , Mikko Alho , Mika Tuomi , Kiia Kallio , Patrick Klas Rudolf Buss , Jari Antero Komppa , Kaj Tuomi
IPC: G06T15/00
Abstract: A system, method and a non-transitory computer readable storage medium are provided for hybrid rendering with deferred primitive batch binning. A primitive batch is generated from one or more primitives. A bin is identified for processing the primitive batch. At least a portion of each primitive intersecting the identified bin is processed and a next bin for processing the primitive batch is identified based on an intercept walk order. The processing is iteratively repeated for the one or more primitives in the primitive batch for successive bins until all primitives of the primitive batch are completely processed. Then, the one or more primitives in the primitive batch are further processed.
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27.发明申请公开(公告)号：US20180121386A1
公开(公告)日：2018-05-03
申请号：US15354560
申请日：2016-11-17
Applicant: Advanced Micro Devices, Inc.
Inventor： Jiasheng Chen , Angel E. Socarras , Michael Mantor , YunXiao Zou , Bin He
IPC: G06F15/80 , G06F9/30 , G06F12/0875 , G06F12/0891
CPC classification number: G06F15/8007 , G06F9/3001 , G06F9/30105 , G06F9/3012 , G06F9/30123 , G06F9/3828 , G06F9/3851 , G06F9/3887 , G06F9/3891 , G06F12/0875 , G06F12/0891 , G06F2212/604
Abstract: A super single instruction, multiple data (SIMD) computing structure and a method of executing instructions in the super-SIMD is disclosed. The super-SIMD structure is capable of executing more than one instruction from a single or multiple thread and includes a plurality of vector general purpose registers (VGPRs), a first arithmetic logic unit (ALU), the first ALU coupled to the plurality of VGPRs, a second ALU, the second ALU coupled to the plurality of VGPRs, and a destination cache (Do$) that is coupled via bypass and forwarding logic to the first ALU, the second ALU and receiving an output of the first ALU and the second ALU. The Do$ holds multiple instructions results to extend an operand by-pass network to save read and write transactions power. A compute unit (CU) and a small CU including a plurality of super-SIMDs are also disclosed.
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公开(公告)号：US20180114290A1
公开(公告)日：2018-04-26
申请号：US15331278
申请日：2016-10-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Timour T. Paltashev , Michael Mantor , Rex Eldon McCrary
Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.
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29.发明授权Method and system for synchronization of workitems with divergent control flow 有权工作单元与发散控制流同步的方法和系统公开(公告)号：US09424099B2
公开(公告)日：2016-08-23
申请号：US13672291
申请日：2012-11-08
Applicant: Advanced Micro Devices, Inc.
Inventor： Michael C. Houston , Benedict R. Gaster , Lee W. Howes , Michael Mantor , Dominik Behr
Abstract: Disclosed methods, systems, and computer program products embodiments include synchronizing a group of workitems on a processor by storing a respective program counter associated with each of the workitems, selecting at least one first workitem from the group for execution, and executing the selected at least one first workitem on the processor. The selecting is based upon the respective stored program counter associated with the at least one first workitem.
Abstract translation: 公开的方法，系统和计算机程序产品实施例包括通过存储与每个工作项相关联的相应程序计数器来同步处理器上的一组工作项，从组中选择至少一个第一工作以供执行，以及执行所选择的至少 处理器上的第一个工作。 所述选择基于与所述至少一个第一工作项相关联的相应存储的程序计数器。
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公开(公告)号：US12205218B2
公开(公告)日：2025-01-21
申请号：US17706811
申请日：2022-03-29
Applicant: ADVANCED MICRO DEVICES, INC.
Inventor： Mark Leather , Michael Mantor
Abstract: A graphics processing unit (GPU) or other apparatus includes a plurality of shader engines. The apparatus also includes a first front end (FE) circuit and one or more second FE circuits. The first FE circuit is configured to schedule geometry workloads for the plurality of shader engines in a first mode. The first FE circuit is configured to schedule geometry workloads for a first subset of the plurality of shader engines and the one or more second FE circuits are configured to schedule geometry workloads for a second subset of the plurality of shader engines in a second mode. In some cases, a partition switch is configured to selectively connect the first FE circuit or the one or more second FE circuits to the second subset of the plurality of shader engines depending on whether the apparatus is in the first mode or the second mode.
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