公开(公告)号：US10529737B2

公开(公告)日：2020-01-07

申请号：US16435887

申请日：2019-06-10

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath

IPC: H01L27/11582 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/10 ,  H01L21/67 ,  H01L21/28

Abstract: Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.

公开(公告)号：US10325923B2

公开(公告)日：2019-06-18

申请号：US15891126

申请日：2018-02-07

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath

IPC: H01L21/28 ,  H01L21/67 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3065 ,  H01L29/10 ,  H01L27/11582

Abstract: Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. The methods further include placing sacrificial polysilicon around the memory hole before forming the bottom stack and removing the sacrificial polysilicon from the slit trench to allow a conducting gapfill to make electrical contact to the polysilicon inside the memory hole.

公开(公告)号：US20180226426A1

公开(公告)日：2018-08-09

申请号：US15891126

申请日：2018-02-07

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath

IPC: H01L27/11582 ,  H01L21/28 ,  H01L21/67

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/67069 ,  H01L29/1037

Abstract: Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. The methods further include placing sacrificial polysilicon around the memory hole before forming the bottom stack and removing the sacrificial polysilicon from the slit trench to allow a conducting gapfill to make electrical contact to the polysilicon inside the memory hole.

公开(公告)号：US20180226425A1

公开(公告)日：2018-08-09

申请号：US15882454

申请日：2018-01-29

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath

IPC: H01L27/11582 ,  H01L21/311 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/10 ,  H01L21/67

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/67069 ,  H01L29/1037

Abstract: Methods of forming 3-d flash memory cells are described. The methods allow the cells to be produced despite a misalignment in at least two sections (top and bottom), each having multiple charge storage locations. The methods include selectively gas-phase etching dielectric from the bottom memory hole portion by delivering the etchants through the top memory hole. Two options for completing the methods include (1) forming a ledge spacer to allow reactive ion etching of the bottom polysilicon portion without damaging polysilicon or charge-trap/ONO layer on the ledge, and (2) placing sacrificial silicon oxide gapfill in the bottom memory hole, selectively forming protective conformal silicon nitride elsewhere, then removing the sacrificial silicon oxide gapfill before performing the reactive ion etching of the bottom polysilicon portion as before.

公开(公告)号：US20160035614A1

公开(公告)日：2016-02-04

申请号：US14448059

申请日：2014-07-31

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Randhir Thakur ,  Shankar Venkataraman ,  Nitin K. Ingle

IPC: H01L21/764 ,  H01L29/06 ,  H01L21/311 ,  H01L29/49 ,  H01L21/02 ,  H01L27/115

CPC classification number: H01L21/764 ,  H01J37/32357 ,  H01L21/02071 ,  H01L21/28273 ,  H01L21/28282 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67103 ,  H01L21/68764 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/66833 ,  H01L29/7887

Abstract: Methods of forming flash memory cells are described which incorporate air gaps for improved performance. The methods are useful for so-called “2-d flat cell” flash architectures. 2-d flat cell flash memory involves a reactive ion etch to dig trenches into multi-layers containing high work function and other metal layers. The methods described herein remove the metal oxide debris from the sidewalls of the multi-layer trench and then, without breaking vacuum, selectively remove shallow trench isolation (STI) oxidation which become the air gaps. Both the metal oxide removal and the STI oxidation removal are carried out in the same mainframe with highly selective etch processes using remotely excited fluorine plasma effluents.

Abstract translation: 描述形成闪速存储器单元的方法，其包括用于改善性能的气隙。 这些方法对于所谓的“2-d平坦单元”闪存架构是有用的。 2-d平板电池闪存包括反应离子蚀刻，以将沟槽挖掘成包含高功函数和其它金属层的多层。 本文描述的方法从多层沟槽的侧壁去除金属氧化物碎屑，然后在不破坏真空的情况下选择性地去除成为气隙的浅沟槽隔离（STI）氧化。 金属氧化物去除和STI氧化去除都是使用远程激发的氟等离子体流出物，在相同的主机中进行高选择性蚀刻工艺。

公开(公告)号：US09136273B1

公开(公告)日：2015-09-15

申请号：US14222418

申请日：2014-03-21

Applicant: Applied Materials, Inc.

Inventor： Vinod R. Purayath ,  Nitin K. Ingle

IPC: H01L21/336 ,  H01L27/115

CPC classification number: H01L29/515 ,  H01J37/32357 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/401 ,  H01L29/4916 ,  H01L29/788

Abstract: Flash memory cells and methods of formation are described for flash memory cells having air gaps through which electrons may pass to alter the charge state of the floating gate. A dummy gate is initially deposited and a polysilicon gate is deposited on the dummy gate. A silicon oxide film is then deposited on the sides of the active area, the dummy gate and the polysilicon. The silicon oxide film holds the polysilicon in place while the dummy gate is selectively etched away. The dummy gate may be doped to increase etch rate. Formerly, silicon oxide was used as a dielectric barrier through which electrons were passed to charge and discharge the floating gate (polysilicon). Eliminating material in the dielectric barrier reduces the tendency to accumulate trapped charges during use and increase the lifespan of flash memory devices.

Abstract translation: 对具有气隙的闪存单元描述闪存单元和形成方法，电子可通过该空隙来改变浮动栅极的电荷状态。 最初沉积一个虚拟栅极，并在该虚拟栅极上沉积多晶硅栅极。 然后在有源区域，伪栅极和多晶硅的侧面上沉积氧化硅膜。 氧化硅膜将多晶硅保持就位，同时选择性地蚀刻掉虚拟栅极。 伪栅极可以被掺杂以增加蚀刻速率。 以前，使用氧化硅作为电子通过电介质势垒来对浮栅（多晶硅）进行充电和放电。 在介质屏障中消除材料减少了在使用过程中积聚陷阱电荷的趋势，并增加了闪存器件的使用寿命。