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    GAME ENGINE APPLICATION DIRECT TO VIDEO ENCODER RENDERING
    21.
    发明申请
    GAME ENGINE APPLICATION DIRECT TO VIDEO ENCODER RENDERING 审中-公开

    公开(公告)号：US20190158704A1

    公开(公告)日：2019-05-23

    申请号：US15816765

    申请日：2017-11-17

    Applicant: ATI Technologies ULC

    Inventor： Gabor Sines ,  Kyle Plumadore ,  Yang Liu ,  Ihab Amer ,  Boris Ivanovic

    IPC: H04N1/60 ,  G06T1/20 ,  G06T9/00 ,  A63F13/5258

    Abstract: Systems, apparatuses, and methods for rendering images directly to a video encoder are disclosed. A game engine includes an embedded rendering unit configured to render images in different color spaces depending on the mode. The rendering unit renders images for a first color space only to be driven directly to a display while operating in a first mode. The rendering unit renders images for a second color space only which are provided directly to a video encoder while operating in a second mode. In a third mode, the rendering unit renders images for both color spaces. In one embodiment, the first color space is RGB and the second color space is YUV. The game engine also generates a plurality of attributes associated with each rendered image and the video encoder encodes each rendered image into an encoded bitstream based on the attributes associated with the rendered image.

    SERVER-BASED ENCODING OF ADJUSTABLE FRAME RATE CONTENT
    22.
    发明申请
    SERVER-BASED ENCODING OF ADJUSTABLE FRAME RATE CONTENT 审中-公开

    公开(公告)号：US20190104311A1

    公开(公告)日：2019-04-04

    申请号：US15721078

    申请日：2017-09-29

    Applicant: ATI Technologies ULC

    Inventor： Ihab Amer ,  Boris Ivanovic ,  Gabor Sines ,  Yang Liu ,  Ho Hin Lau ,  Haibo Liu ,  Kyle Plumadore

    IPC: H04N19/137 ,  H04N19/115

    Abstract: Systems, apparatuses, and methods for encoding bitstreams of uniquely rendered video frames with variable frame rates are disclosed. A rendering unit and an encoder in a server are coupled via a network to a client with a decoder. The rendering unit dynamically adjusts the frame rate of uniquely rendered frames. Depending on the embodiment, the rendering unit conveys a constant frame rate to the encoder by repeating some frames or the rendering unit conveys a variable frame rate to the encoder by conveying only uniquely rendered frames to the encoder. Depending on the embodiment, the encoder conveys a constant frame rate bitstream to the decoder by encoding repeated frames as skip frames, or the encoder conveys a variable frame rate bitstream to the decoder by dropping repeated frames from the bitstream.

    Graphics rendering with encoder feedback
    25.
    发明授权
    Graphics rendering with encoder feedback 有权

    公开(公告)号：US11830225B2

    公开(公告)日：2023-11-28

    申请号：US15993074

    申请日：2018-05-30

    Applicant: ATI TECHNOLOGIES ULC

    Inventor： Yang Liu ,  Ihab Amer ,  Gabor Sines ,  Boris Ivanovic ,  Jinbo Qiu

    IPC: G06T9/00 ,  G06T15/00

    CPC classification number: G06T9/00 ,  G06T15/005 ,  G06T2210/08 ,  G06T2210/36

    Abstract: A feedback processing module includes a memory configured to store feedback received from an encoder. The feedback includes parameters associated with encoded graphics content generated by a graphics engine. The feedback processing module also includes a processor configured to generate configuration information for the graphics engine based on the feedback. The graphics engine is configured to execute a workload based on the configuration information. In some cases, the feedback processing module is also configured to receive feedback from a decoder that is used to decode the graphics content that is encoded by the encoder and generate the configuration information based on the feedback received from the decoder.

    Performing asynchronous memory clock changes on multi-display systems
    26.
    发明授权
    Performing asynchronous memory clock changes on multi-display systems 有权

    公开(公告)号：US11699408B2

    公开(公告)日：2023-07-11

    申请号：US17131209

    申请日：2020-12-22

    Applicant: ATI Technologies ULC

    Inventor： Arshad Rahman ,  Rajeevan Panchacharamoorthy ,  Boris Ivanovic

    IPC: G09G3/36 ,  G09G5/00 ,  G11C7/22 ,  G11C7/10

    CPC classification number: G09G3/3618 ,  G09G5/001 ,  G09G5/006 ,  G11C7/1072 ,  G11C7/222

    Abstract: Systems, apparatuses, and methods for performing asynchronous memory clock changes on multiple displays are disclosed. From time to time, a memory clock frequency change is desired for a memory subsystem storing frame buffer(s) used to drive pixels to multiple displays. For example, when the real-time memory bandwidth demand differs from the memory bandwidth available with the existing memory clock frequency, a control unit tracks the vertical blanking interval (VBI) timing of a first display. Also, the control unit causes a second display to enter into panel self-refresh (PSR) mode. Once the PSR mode of the second display overlaps with a VBI of the first display, a memory clock frequency change, including memory training, is initiated. After the memory clock frequency change, the displays are driven by the frame buffer(s) in the memory subsystem at an updated frequency.

    SPATIAL BLOCK-LEVEL PIXEL ACTIVITY EXTRACTION OPTIMIZATION LEVERAGING MOTION VECTORS
    29.
    发明申请
    SPATIAL BLOCK-LEVEL PIXEL ACTIVITY EXTRACTION OPTIMIZATION LEVERAGING MOTION VECTORS 有权

    公开(公告)号：US20210243450A1

    公开(公告)日：2021-08-05

    申请号：US17236910

    申请日：2021-04-21

    Applicant: ATI Technologies ULC

    Inventor： Mehdi Saeedi ,  Boris Ivanovic

    IPC: H04N19/14 ,  H04N19/513 ,  H04N19/176

    Abstract: Systems, apparatuses, and methods for implementing spatial block-level pixel activity extraction optimization leveraging motion vectors are disclosed. Control logic coupled to an encoder generates block-level pixel activity metrics for a new frame based on the previously calculated block-level pixel activity data from a reference frame. A cost is calculated for each block of a new frame with respect to a corresponding block of the reference frame. If the cost is less than a first threshold, then the control logic generates an estimate of a pixel activity metric for the block which is equal to a previously calculated pixel activity metric for a corresponding block of the reference frame. If the cost is greater than the first threshold but less than a second threshold, an estimate of the pixel activity metric is generated by extrapolating from the previously calculated pixel activity metric.

    RESIDUAL METRICS IN ENCODER RATE CONTROL SYSTEM
    30.
    发明申请
    RESIDUAL METRICS IN ENCODER RATE CONTROL SYSTEM 有权

    公开(公告)号：US20210185313A1

    公开(公告)日：2021-06-17

    申请号：US16715187

    申请日：2019-12-16

    Applicant: ATI Technologies ULC

    Inventor： Boris Ivanovic ,  Mehdi Saeedi

    IPC: H04N19/115 ,  G06N5/04 ,  H04N19/176 ,  H04N19/159

    Abstract: Systems, apparatuses, and methods for using residual metrics for encoder rate control are disclosed. An encoder includes a mode decision unit for determining a mode to be used for generating a predictive block for each block of a video frame. For each block, control logic calculates a residual of the block by comparing an original version of the block to the predictive block. The control logic generates a residual metric based on the residual and based on the mode. The encoder's rate controller selects a quantization strength setting for the block based on the residual metric. Then, the encoder generates an encoded block that represents the input block by encoding the block with the selected quantization strength setting. Next, the encoder conveys the encoded block to a decoder to be displayed. The encoder repeats this process for each block of the frame.

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