公开(公告)号：US07283609B2

公开(公告)日：2007-10-16

申请号：US11164101

申请日：2005-11-10

申请人： George E. Possin ,  Jonathan D. Short ,  Wen Li

发明人： George E. Possin ,  Jonathan D. Short ,  Wen Li

IPC分类号： G01N23/083 ,  H05G1/64 ,  G01T1/24 ,  H01L27/14

CPC分类号： G01T1/2018 ,  A61B6/032

摘要： A CT detector includes a pixel having a single photodiode and multiple charge storage devices that are alternately stored and read out. The photodiode is a frontlit diode with a pair of capacitors that alternately store charge generated during data acquisition. Multiple pixels are connected to a single readout amplifier. Charge is continuously acquired from each photodiode and stored on the charge storage devices, but such readout is from a single charge storage device at a time. As such, each charge storage device is read out independently, but the charge storage devices are connected to a common readout channel or port.

摘要翻译： CT检测器包括具有单个光电二极管的像素和交替存储和读出的多个电荷存储装置。 光电二极管是具有一对电容器的前照明二极管，其交替地存储在数据采集期间产生的电荷。 多个像素连接到单个读出放大器。 从每个光电二极管连续获取电荷并将其存储在电荷存储装置上，但这样的读出是从一个电荷存储装置一次。 因此，每个电荷存储装置被独立地读出，但是电荷存储装置连接到公共读出通道或端口。

公开(公告)号：US5616524A

公开(公告)日：1997-04-01

申请号：US580094

申请日：1995-12-22

申请人： Ching Y. Wei ,  Jianqiang Liu ,  Roger S. Salisbury ,  Robert F. Kwasnick ,  George E. Possin ,  Douglas Albagli

发明人： Ching Y. Wei ,  Jianqiang Liu ,  Roger S. Salisbury ,  Robert F. Kwasnick ,  George E. Possin ,  Douglas Albagli

IPC分类号： H01L21/66 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/52 ,  H01L27/146 ,  H01L21/465

CPC分类号： H01L21/76892 ,  Y10T29/49162

摘要： A method of repairing an open circuit defect in a damaged address line in a thin film electronic imager device includes the steps of forming a repair area on the device so as to expose the open-circuit defect in the damaged address line and then depositing a conductive material to form a second conductive component and to coincidentally form a repair shunt in the repair area so as to electrically bridge the defect. The step of forming the repair area includes the steps of ablating dielectric material disposed over the first conductive component in the repair area, and etching the repair area so as to remove dielectric material disposed over the defect in the address line in the repair area such that the surface of the address line conductive material is exposed but is not contaminated by the removal of the overlying dielectric material. A layer of photoresist is deposited over the imager device prior to forming the repair area, such that the photoresist layer is patterned during the ablating step and serves as a mask during the etch step.

摘要翻译： 在薄膜电子成像装置中修复损坏的地址线中的开路缺陷的方法包括以下步骤：在设备上形成修复区域，以暴露损坏的地址线中的开路缺陷，然后沉积导电 材料以形成第二导电部件并且在修复区域中巧合地形成修复分路，从而电连接缺陷。 形成修复区域的步骤包括以下步骤：消除设置在修复区域中的第一导电部件上的介电材料，并蚀刻修复区域，以便去除在修复区域中的地址线上的缺陷上的介电材料，使得 地址线导电材料的表面被暴露，但不会被除去上覆电介质材料污染。 在形成修复区域之前，在成像器装置上沉积一层光致抗蚀剂，使得光刻胶层在烧蚀步骤期间被图案化，并在蚀刻步骤期间用作掩模。

公开(公告)号：US5610404A

公开(公告)日：1997-03-11

申请号：US523324

申请日：1995-09-05

申请人： George E. Possin

发明人： George E. Possin

IPC分类号： G01T1/20 ,  H01L27/14 ,  H01L27/146 ,  H04N5/32 ,  H01L31/0224 ,  G01T1/24

CPC分类号： H01L27/14643

摘要： A flat panel radiation imaging device that exhibits reduced capacitive coupling between pixel photodiodes and readout data lines, and thus in operation has reduced phantom images and image artifacts, includes a ground plane electrode that is disposed between the substrate and the plurality of pixels arranged in an imaging array pattern. The ground plane electrode is a conductive material layer that is disposed in a continuous sheet underlying the imaging array pattern; alternatively, the ground plane is a patterned sheet of conductive material having data line cutout areas disposed so that no ground plane conductive material underlies or is closer than a lateral set off distance from data lines in the imaging array pattern. A patterned ground plane further may include pixel electrode cutout sections disposed such that ground plane conductive material underlies pixel electrodes in the imaging array pattern only by a selected overlap distance around the boundaries of the pixel electrode.

摘要翻译： 在像素光电二极管和读出数据线之间呈现出减小的电容耦合并因此在操作中的平板辐射成像装置具有减少的幻影图像和图像伪像，包括设置在基板和布置在基板之间的多个像素之间的接地平面电极 成像阵列图案。 接地平面电极是布置在成像阵列图案下方的连续薄片中的导电材料层; 接地平面是导电材料的图案片，其具有设置成没有接地平面导电材料位于或远离与成像阵列图案中的数据线的横向偏离距离的数据线切口区域。 图案化接地平面还可以包括像素电极切除部分，其设置成使得接地平面导电材料仅在像素电极的边界周围的选定的重叠距离处在成像阵列图案中的像素电极之下。

公开(公告)号：US5541128A

公开(公告)日：1996-07-30

申请号：US533406

申请日：1995-09-25

申请人： Robert F. Kwasnick ,  George E. Possin

发明人： Robert F. Kwasnick ,  George E. Possin

IPC分类号： H01L29/78 ,  H01L21/033 ,  H01L21/336 ,  H01L29/786 ,  H01L21/86

CPC分类号： H01L29/78696 ,  H01L21/0331 ,  H01L29/66765 ,  H01L29/78669 ,  Y10S148/10 ,  Y10S438/951

摘要： In the fabrication of thin-film field-effect transistors, a dielectric island is first formed over a gate and between locations where source and drain contacts are to be deposited. A dielectric cap with an overhanging brim is formed on the island. A layer of SD metal which will form the source-drain contacts is next deposited. Because of the overhang, the SD metal does not coat the entire cap, but leaves part of the cap remaining exposed and attackable by an etchant. Application of an etchant etches away the island and the cap, thereby lifting off the SD metal coated on the cap, leaving the fully-formed source and drain contacts in place, separated by the extent of the island.

摘要翻译： 在薄膜场效应晶体管的制造中，电介质岛首先形成在栅极上以及在源极和漏极接触物将被沉积的位置之间。 在岛上形成具有突出边缘的电介质盖。 接下来沉积将形成源极 - 漏极触点的SD金属层。 由于悬垂，SD金属不覆盖整个盖子，而是使盖子的一部分保持暴露并被腐蚀剂侵袭。 蚀刻剂的应用蚀刻掉岛和盖，从而剥离涂覆在盖上的SD金属，使得完全形成的源极和漏极触点留在适当位置，由岛的范围分开。

公开(公告)号：US5324674A

公开(公告)日：1994-06-28

申请号：US43999

申请日：1993-04-05

申请人： George E. Possin ,  Ching-Yeu Wei

发明人： George E. Possin ,  Ching-Yeu Wei

IPC分类号： H01L21/336 ,  H01L21/77 ,  H01L21/84 ,  H01L29/786 ,  H01L21/265

CPC分类号： H01L29/78696 ,  H01L27/1214 ,  H01L29/66765 ,  Y10S438/978

摘要： A thin film transistor (TFT) having reduced end leakage is fabricated by: forming a gate electrode on a substrate; forming a TFT body disposed over the gate electrode, the TFT body comprising an intrinsic semiconductor material layer, a channel plug disposed on the intrinsic semiconductor material layer over the gate electrode, a doped semiconductor material layer on the intrinsic semiconductor material and the sidewalls of the channel plug, and a source/drain metallization layer; selectively etching the source/drain metallization layer to form an address connection line and a pixel connection line to a respective source electrode tip and drain electrode tip, selectively etching the channel plug to remove the portion of the sidewalls not adjoining the source and electrode tips that had been in contact with the doped semiconductor layer; removing the doped semiconductor layer portion not underlying the address connection line, the pixel connection line, and the source and drain electrode tips; and removing the now-exposed portion of the intrinsic semiconductor layer material that had been in contact with the doped semiconductor material.

摘要翻译： 通过在基板上形成栅电极来制造具有减少的端漏的薄膜晶体管（TFT） 形成设置在所述栅电极上的TFT体，所述TFT体包括本征半导体材料层，设置在所述栅电极上的所述本征半导体材料层上的沟道插塞，所述本征半导体材料上的掺杂半导体材料层和所述本体半导体材料的侧壁 沟道插塞和源极/漏极金属化层; 选择性地蚀刻源极/漏极金属化层以形成地址连接线和到相应的源极电极尖端和漏极电极尖端的像素连接线，选择性地蚀刻沟道插塞以去除不邻接源极和电极尖端的侧壁部分， 已经与掺杂半导体层接触; 去除不在地址连​​接线下方的掺杂半导体层部分，像素连接线以及源极和漏极电极尖端; 以及去除已经与掺杂半导体材料接触的本征半导体层材料的现在曝光部分。

公开(公告)号：US5148248A

公开(公告)日：1992-09-15

申请号：US303091

申请日：1989-01-26

申请人： George E. Possin ,  Harold G. Parks ,  Jack D. Kingsley

发明人： George E. Possin ,  Harold G. Parks ,  Jack D. Kingsley

IPC分类号： H01L27/12

CPC分类号： H01L27/12

摘要： A dual dielectric structure is employed in the fabrication of thin film field effect transistors in a matrix addressed liquid display to provide improved transistor device characteristics and also to provide both electricial and chemical isolation for material employed in the gate metallization layer. In particular, the use of a layer of silicon oxide over the gate metallization layer is not only consistent with providing the desired electrical and chemical isolation, but also with providing redundant gate metallization material to be employed beneath source or data lines for electrical circuit redundancy. Gate line redundancy is also possible. The electrical and chemical isolation provided by the dual dielectric layer reduces the possibilities of short circuits occurring in the display. The absence of short circuits together with the improved redundancy characteristics significantly increase manufacturing yield. As display sizes increase, the yield problem becomes more and more significant, generally growing as the square of the diagonal measurement of the screen. The structure in the present invention also significantly reduces gate leakage current. In the process and structure of the present invention, gate electrode material is separated from semiconductor material by the aforementioned dual dielectric, typically comprising layers of silicon oxide disposed beneath a layer of silicon nitride which is, in turn, disposed beneath the active amorphous silicon semiconductor material.

摘要翻译： 在矩阵寻址的液体显示器中制造薄膜场效应晶体管时采用双电介质结构以提供改进的晶体管器件特性，并且还为栅极金属化层中使用的材料提供电化学和化学隔离。 特别地，在栅极金属化层上使用一层氧化硅不仅与提供期望的电和化学隔离一致，而且还提供要用于电路冗余的源极或数据线下方的冗余栅极金属化材料。 栅线冗余也是可能的。 由双电介质层提供的电气和化学隔离减少了在显示器中发生短路的可能性。 没有短路以及改进的冗余特性显着提高了制造产量。 随着显示尺寸的增加，产量问题变得越来越重要，通常随屏幕对角线测量的平方而增长。 本发明的结构也显着地降低了栅极漏电流。 在本发明的方法和结构中，栅极电极材料通过上述双电介质与半导体材料分离，所述双电介质通常包括设置在有源非晶硅半导体下方的氮化硅层下方的氧化硅层 材料。

公开(公告)号：US5130263A

公开(公告)日：1992-07-14

申请号：US510767

申请日：1990-04-17

申请人： George E. Possin ,  Siegfried Aftergut

发明人： George E. Possin ,  Siegfried Aftergut

IPC分类号： G02F1/136 ,  G02F1/1368 ,  G03F7/039 ,  G03F7/26 ,  H01L21/027 ,  H01L21/30 ,  H01L21/336 ,  H01L29/786

CPC分类号： H01L29/66765 ,  H01L21/0274

摘要： A method for photolithographically forming a mask includes the steps of: forming an island structure of opaque material on a principal surface of a transparent substrate; depositing at least one layer of transparent material on the principal substrate surface and over the island structure; depositing a layer of photoresist material over the at least one transparent layer; exposing a back-side substrate surface, opposite to the principal substrate surface, to UV light to cause exposure of at least a portion of the photoresist, corresponding substantially to an area outside of a shadow of the island structure; reflecting at least a portion of UV light back into the photoresist layer, by depositing a non-specular layer over the photoresist layer before UV exposure, to expose another portion of the photoresist layer a selected overlap distance within the island structure shadow; and removing the exposed photoresist portion to form a mask which is aligned with the island structure and narrower than the island structure by the selected overlap distance on each side thereof.

公开(公告)号：US4704623A

公开(公告)日：1987-11-03

申请号：US761981

申请日：1985-08-02

申请人： William W. Piper ,  George E. Possin

发明人： William W. Piper ,  George E. Possin

IPC分类号： H01L29/78 ,  G02F1/136 ,  G02F1/1368 ,  G09F9/35 ,  H01L27/12 ,  H01L29/417 ,  H01L29/786

CPC分类号： H01L29/78696 ,  H01L29/78618 ,  H01L29/78669

摘要： An amorphous silicon thin film FET is doped and structured to be particularly useful for use in liquid crystal display circuits. In particular, critical FET dimensions are provided along with doping levels and locations which permit optimal reduction of source to gate capacitance, while at the same time, preventing the occurrence of large contact voltage drops. Critical dimensions include active channel length, source-gate overlap, and amorphous silicon thickness. A critical relationship is established amongst these parameters and amorphous silicon doping levels.

摘要翻译： 非晶硅薄膜FET被掺杂并构造成特别适用于液晶显示电路。 特别地，临界FET尺寸与掺杂水平和位置一起提供，这些掺杂水平和位置允许最佳地将源极降低到栅极电容，同时防止大的接触电压降的发生。 关键尺寸包括有源沟道长度，源栅重叠和非晶硅厚度。 在这些参数和非晶硅掺杂水平之间建立了关键的关系。

公开(公告)号：US4099261A

公开(公告)日：1978-07-04

申请号：US770698

申请日：1977-02-22

申请人： Conilee G. Kirkpatrick ,  George E. Possin

发明人： Conilee G. Kirkpatrick ,  George E. Possin

IPC分类号： G11C13/04 ,  G11C13/00

CPC分类号： G11C13/048

摘要： A method for storing data in an archival memory semiconductor target by inducing damage to the semiconductor lattice at selected ones of a plurality of storage sites arranged as a two-dimensional array upon a surface of the target. Ions are accelerated and collimated as a beam to impinge upon a target surface to induce the damage to a controlled depth, whereby subsequent illumination of a damaged data site by an electron beam will allow the beam-produced electron-hole pairs to recombine within the damaged area to prevent increased current flow and read a binary zero bit, while hole migrations through a target depletion region will cause increased current flow, at an undamaged data site, to indicate a binary one data bit.

摘要翻译： 一种用于通过在目标表面上排列成二维阵列的多个存储位置中的选定的存储位置处引起对半导体栅格的损坏来将数据存储在归档存储器半导体目标物中的方法。 离子被加速和准直，作为射束撞击在目标表面上以引起受控深度的损伤，由此电子束随后照射损坏的数据位置将允许射束产生的电子 - 空穴对在损坏的内部重组 区域以防止增加的电流流动并读取二进制零位，而通过目标耗尽区域的空穴迁移将导致在未损坏数据站点处的增加的电流流动以指示二进制一个数据位。

公开(公告)号：US07403589B1

公开(公告)日：2008-07-22

申请号：US11691959

申请日：2007-03-27

申请人： Jonathan D. Short ,  George E. Possin ,  James W. LeBlanc ,  Rogerio G. Rodrigues ,  Kent C. Burr ,  Aaron J. Couture ,  Wen Li

发明人： Jonathan D. Short ,  George E. Possin ,  James W. LeBlanc ,  Rogerio G. Rodrigues ,  Kent C. Burr ,  Aaron J. Couture ,  Wen Li

IPC分类号： A61B6/00

CPC分类号： A61B6/482 ,  A61B6/032 ,  A61B6/4241 ,  G01T1/1642 ,  G01T1/2018

摘要： A detector module for a CT imaging system includes a scintillator to convert x-rays to optical photons. The scintillator is optically coupled to a solid-state photomultiplier with internal gain to receive the optical photons and convert them into a corresponding electrical signal output.

摘要翻译： 用于CT成像系统的检测器模块包括将X射线转换成光学光子的闪烁体。 闪烁体与具有内部增益的固态光电倍增管光学耦合，以接收光学光子并将其转换成相应的电信号输出。