公开(公告)号：US12072754B2

公开(公告)日：2024-08-27

申请号：US17485199

申请日：2021-09-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Benjamin Tsien ,  Mihir Shaileshbhai Doctor ,  Stephen V. Kosonocky ,  John P. Petry ,  Thomas J. Gibney

IPC: G06F1/00 ,  G06F1/3296

CPC classification number: G06F1/3296

Abstract: A method and apparatus for managing a controller includes indicating, by a processor of a first device, to the controller of a second device to enter a second power state from a first power state. The controller of the second device responds to the processor of the first device with a confirmation. The processor of the first device transmits a signal to the controller of the second device to enter the second power state. Upon receiving a wake event, the controller of the second device exits the second device from the second power state to the first power state.

公开(公告)号：US11947476B2

公开(公告)日：2024-04-02

申请号：US17710413

申请日：2022-03-31

Applicant: Advanced Micro Devices, Inc.

Inventor： Bryan Broussard ,  Pravesh Gupta ,  Benjamin Tsien ,  Vydhyanathan Kalyanasundharam

IPC: G06F13/20

CPC classification number: G06F13/20 ,  G06F2213/40

Abstract: Methods and systems are disclosed for cross-chiplet performance data streaming. Techniques disclosed include accumulating, by a subservient chiplet, event data associated with an event indicative of a performance aspect of the subservient chiplet; sending, by the subservient chiplet, the event data over a chiplet bus to a master chiplet; and adding, by the master chiplet, the received event data to an event record, the event record containing previously received, from the subservient chiplet over the chiplet bus, event data associated with the event.

公开(公告)号：US11899520B2

公开(公告)日：2024-02-13

申请号：US17730041

申请日：2022-04-26

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Ashish Jain ,  Benjamin Tsien ,  Chintan S. Patel ,  Vydhyanathan Kalyanasundharam ,  Shang Yang

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3234 ,  G06F12/0891

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0891 ,  G06F2212/1021 ,  G06F2212/1028

Abstract: A technique for operating a cache is disclosed. The technique includes in response to a power down trigger that indicates that the cache effectiveness is considered to be low, powering down the cache.

公开(公告)号：US20240004821A1

公开(公告)日：2024-01-04

申请号：US17853812

申请日：2022-06-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael J. Tresidder ,  Benjamin Tsien

IPC: G06F13/40 ,  G06F1/26

CPC classification number: G06F13/4004 ,  G06F1/26 ,  G06F2213/40

Abstract: Systems and methods are disclosed for voltage droop mitigation associated with a voltage rail that supplies power to circuitry of a chiplet. Techniques disclosed include detecting an upcoming transmission of data packets that are to be transmitted through a physical layer of the chiplet. Then, before transmitting the data packets through the physical layer, throttling a rate of bandwidth utilization in the physical layer and transmitting, by the controller, the data packets through the physical layer.

公开(公告)号：US11703937B2

公开(公告)日：2023-07-18

申请号：US17483698

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Mihir Shaileshbhai Doctor ,  Alexander J. Branover ,  Benjamin Tsien ,  Indrani Paul ,  Christopher T. Weaver ,  Thomas J. Gibney ,  Stephen V. Kosonocky ,  John P. Petry

IPC: G06F1/32 ,  G06F1/3287 ,  G06F1/3296 ,  G06F1/3234

CPC classification number: G06F1/3287 ,  G06F1/3265 ,  G06F1/3278 ,  G06F1/3296

Abstract: Devices and methods for linear addressing are provided. A device is provided which comprises a plurality of components having assigned registers used to store data to execute a program and a power management controller, in communication with the components. The power management controller is configured to send one of a request to remove power to the components and a request to reduce power to the components when it is determined that the components are idle, execute a first process of one of removing power and reducing power to the components and entering a reduced power state when an acknowledgement of the request is received and execute a second process of restoring power to the components when one or more of the components are indicated to be active.

公开(公告)号：US20230090126A1

公开(公告)日：2023-03-23

申请号：US17483694

申请日：2021-09-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Christopher T. Weaver ,  Indrani Paul ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Thomas J. Gibney ,  Jose G. Cruz ,  Pravesh Gupta ,  Chintan S. Patel

IPC: G06F1/3234 ,  G06F11/14 ,  G06F3/06

Abstract: Devices and methods for transitioning between power states of a device are provided. A program is executed using data stored in configuration registers assigned to a component of a device. For a first reduced power state, data of a first portion of the configuration registers is saved to the memory using a first set of linear address space. For a second reduced power state, data of a second portion of the configuration registers is saved to the memory using a second set of linear address space and data of a third portion of the configuration registers is saved to the memory using a third set of linear address space.

公开(公告)号：US20230031388A1

公开(公告)日：2023-02-02

申请号：US17390429

申请日：2021-07-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Indrani Paul ,  Alexander J. Branover ,  Thomas J. Gibney ,  Mihir Shaileshbhai Doctor ,  John P. Petry ,  Stephen V. Kosonocky ,  Christopher T. Weaver

IPC: G06F1/3203

Abstract: Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.

公开(公告)号：US20210333860A1

公开(公告)日：2021-10-28

申请号：US17366423

申请日：2021-07-02

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Greggory D. Donley ,  Bryan P. Broussard

IPC: G06F1/3287 ,  G06F9/50 ,  G06F1/3209 ,  G06F1/3234 ,  G06F1/3296

Abstract: Systems, apparatuses, and methods for performing efficient power management for a multi-node computing system are disclosed. A computing system includes multiple nodes. When power down negotiation is distributed, negotiation for system-wide power down occurs within a lower level of a node hierarchy prior to negotiation for power down occurring at a higher level of the node hierarchy. When power down negotiation is centralized, a given node combines a state of its clients with indications received on its downstream link and sends an indication on an upstream link based on the combining. Only a root node sends power down requests.

公开(公告)号：US20210090613A1

公开(公告)日：2021-03-25

申请号：US17113322

申请日：2020-12-07

Applicant: Advanced Micro Devices, Inc.

Inventor： Benjamin Tsien ,  Alexander J. Branover ,  Alan Dodson Smith ,  Chintan S. Patel

IPC: G11C5/06 ,  G06F1/3296 ,  G06F13/40 ,  G06F1/3234 ,  G06F1/3203 ,  G06F1/3287 ,  G11C5/02 ,  G11C5/14

Abstract: Systems, apparatuses, and methods for implementing dynamic control of a multi-region fabric are disclosed. A system includes at least one or more processing units, one or more memory devices, and a communication fabric coupled to the processing unit(s) and memory device(s). The system partitions the fabric into multiple regions based on different traffic types and/or periodicities of the clients connected to the regions. For example, the system partitions the fabric into a stutter region for predictable, periodic clients and a non-stutter region for unpredictable, non-periodic clients. The system power-gates the entirety of the fabric in response to detecting a low activity condition. After power-gating the entirety of the fabric, the system periodically wakes up one or more stutter regions while keeping the other non-stutter regions in power-gated mode. Each stutter region monitors stutter client(s) for activity and processes any requests before going back into power-gated mode.

公开(公告)号：US10474211B2

公开(公告)日：2019-11-12

申请号：US15663464

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Sonu Arora ,  Alexander Branover ,  Benjamin Tsien

IPC: G06F1/00 ,  G06F1/26 ,  G06F13/16

Abstract: A data processing system includes a power manager for providing a power event depth signal in response to a power event request signal. A plurality of real-time clients is coupled to the power manager. Each real-time client includes a client buffer that has a plurality of entries for storing data. The real-time client also includes a register for storing a watermark threshold for the client buffer, as well as logic for providing an allow signal when a number of valid entries in the client buffer exceeds the watermark threshold. A power management state machine is coupled to each of the plurality of real-time clients. The power management state machine provides a power event start signal in response to all of the plurality of real-time clients providing respective allow signals.