中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

99 records (took 0.026 seconds)

    HYBRID RENDER WITH PREFERRED PRIMITIVE BATCH BINNING AND SORTING
    22.
    发明申请
    HYBRID RENDER WITH PREFERRED PRIMITIVE BATCH BINNING AND SORTING 审中-公开
    混合渲染与优选的初步批量结合和分类

    公开(公告)号：US20160371873A1

    公开(公告)日：2016-12-22

    申请号：US15250357

    申请日：2016-08-29

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Michael Mantor ,  Laurent Lefebvre ,  Mikko Alho ,  Mika Tuomi ,  Kiia Kallio

    IPC: G06T15/00 ,  G06T15/80 ,  G06T17/20 ,  G06T15/04

    CPC classification number: G06T15/005 ,  G06T15/04

    Abstract: A system, method and a computer program product are provided for hybrid rendering with deferred primitive batch binning A primitive batch is generated from a sequence of primitives. Initial bin intercepts are identified for primitives in the primitive batch. A bin for processing is identified. The bin corresponds to a region of a screen space. Pixels of the primitives intercepting the identified bin are processed. Next bin intercepts are identified while the primitives intercepting the identified bin are processed.

    Abstract translation: 提供了一种系统，方法和计算机程序产品，用于具有延迟原始批量分组的混合渲染。从原始序列生成原始批次。 初始批次拦截中的原始字符串标识。 识别用于处理的仓。 该箱对应于屏幕空间的一个区域。 处理识别的仓的图元的像素。 识别旁边的截距，同时处理拦截识别的bin的原语。

    CONVOLUTIONAL NEURAL NETWORK OPERATIONS
    24.
    发明申请
    CONVOLUTIONAL NEURAL NETWORK OPERATIONS 有权

    公开(公告)号：US20230097279A1

    公开(公告)日：2023-03-30

    申请号：US17489734

    申请日：2021-09-29

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Brian Emberling ,  Michael Mantor ,  Michael Y. Chow ,  Bin He

    IPC: G06N3/04 ,  G06F9/38 ,  G06F17/16

    Abstract: Methods and systems are disclosed for executing operations on single-instruction-multiple-data (SIMD) units. Techniques disclosed perform a dot product operation on input data during one computer cycle, including convolving the input data, generating intermediate data, and applying one or more transitional operations to the intermediate data to generate output data. Aspects described, wherein the input data is an input to a layer of a convolutional neural network and the generated output data is the output of the layer.

    Pairing SIMD lanes to perform double precision operations
    25.
    发明授权
    Pairing SIMD lanes to perform double precision operations 有权

    公开(公告)号：US11409536B2

    公开(公告)日：2022-08-09

    申请号：US15342809

    申请日：2016-11-03

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Bin He ,  YunXiao Zou ,  Jiasheng Chen ,  Michael Mantor

    IPC: G06F9/38 ,  G06F9/30

    Abstract: A method and apparatus for performing a multi-precision computation in a plurality of arithmetic logic units (ALUs) includes pairing a first Single Instruction/Multiple Data (SIMD) block channel device with a second SIMD block channel device to create a first block pair having one-level staggering between the first and second channel devices. A third SIMD block channel device is paired with a fourth SIMD block channel device to create a second block pair having one-level staggering between the third and fourth channel devices. A plurality of source inputs are received at the first block pair and the second block pair. The first block pair computes a first result, and the second block pair computes a second result.

    BROADCAST SYNCHRONIZATION FOR DYNAMICALLY ADAPTABLE ARRAYS
    26.
    发明申请
    BROADCAST SYNCHRONIZATION FOR DYNAMICALLY ADAPTABLE ARRAYS 有权

    公开(公告)号：US20220197655A1

    公开(公告)日：2022-06-23

    申请号：US17548105

    申请日：2021-12-10

    Applicant: ADVANCED MICRO DEVICES, INC.

    Inventor： Sateesh LAGUDU ,  Arun Vaidyanathan ANANTHANARAYAN ,  Michael Mantor ,  Allen H. Rush

    IPC: G06F9/32 ,  G06F9/30 ,  G06F15/80

    Abstract: An array processor includes processor element arrays (PEAs) distributed in rows and columns. The PEAs are configured to perform operations on parameter values. A first sequencer received a first direct memory access (DMA) instruction that includes a request to read data from at least one address in memory. A texture address (TA) engine requests the data from the memory based on the at least one address and a texture data (TD) engine provides the data to the PEAs. The PEAs provide first synchronization signals to the TD engine to indicate availability of registers for receiving the data. The TD engine provides second synchronization signals to the first sequencer in response to receiving acknowledgments that the PEAs have consumed the data.

    Split frame rendering
    27.
    发明授权
    Split frame rendering 有权

    公开(公告)号：US10922868B2

    公开(公告)日：2021-02-16

    申请号：US16452831

    申请日：2019-06-26

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Mangesh P. Nijasure ,  Todd Martin ,  Michael Mantor

    IPC: G06T15/00 ,  G06F9/44 ,  G06T11/40

    Abstract: Improvements in the graphics processing pipeline that allow multiple pipelines to cooperate to render a single frame are disclosed. Two approaches are provided. In a first approach, world-space pipelines for the different graphics processing pipelines process all work for draw calls received from a central processing unit (CPU). In a second approach, the world-space pipelines divide up the work. Work that is divided is synchronized and redistributed at various points in the world-space pipeline. In either approach, the triangles output by the world-space pipelines are distributed to the screen-space pipelines based on the portions of the render surface overlapped by the triangles. Triangles are rendered by screen-space pipelines associated with the render surface portions overlapped by those triangles.

    Memory protection in highly parallel computing hardware
    29.
    发明授权
    Memory protection in highly parallel computing hardware 有权

    公开(公告)号：US10372522B2

    公开(公告)日：2019-08-06

    申请号：US15582443

    申请日：2017-04-28

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Carlos Sampayo ,  Michael Mantor

    IPC: G06F11/00 ,  G06F11/07 ,  G06F9/38

    Abstract: Techniques for handling memory errors are disclosed. Various memory units of an accelerated processing device (“APD”) include error units for detecting errors in data stored in the memory (e.g., using parity protection or error correcting code). Upon detecting an error considered to be an “initial uncorrectable error,” the error unit triggers transmission of an initial uncorrectable error interrupt (“IUE interrupt”) to a processor. This IUE interrupt includes information identifying the specific memory unit in which the error occurred (and possible other information about the error). A halt interrupt is generated and transmitted to the processor in response to the data having the error being consumed (i.e., used by an operation such as an instruction or command), which causes the APD to halt operations. If the data having the error is not consumed, then the halt interrupt is never generated (that the error occurred may remain logged, however).

Patent Agency Ranking