公开(公告)号：US08030964B1

公开(公告)日：2011-10-04

申请号：US12121028

申请日：2008-05-15

Applicant: Shou-Po Shih ,  Weiqi Ding ,  Juei-Chu Tu

Inventor： Shou-Po Shih ,  Weiqi Ding ,  Juei-Chu Tu

IPC: H03K19/0175

CPC classification number: H03K19/018521

Abstract: A level shifter circuit includes an input circuit, an inverter, a pull-up circuit, and a pull-down circuit. The input circuit generates a pull-up signal in response to an input signal using charge from a supply voltage. The inverter inverts the input signal to generate a pull-down signal. The inverter comprises complementary transistors that receive charge from the supply voltage. The pull-up circuit pulls a level shifted output signal of the level shifter circuit to the supply voltage in response to the pull-up signal. The pull-down circuit pulls the level shifted output signal to a low voltage in response to the pull-down signal.

Abstract translation: 电平移位电路包括输入电路，反相器，上拉电路和下拉电路。 输入电路响应于使用来自电源电压的电荷的输入信号产生上拉信号。 反相器反相输入信号产生下拉信号。 反相器包括从电源电压接收电荷的互补晶体管。 上拉电路响应于上拉信号将电平移位器电路的电平移位输出信号拉到电源电压。 下拉电路响应于下拉信号将电平移位的输出信号拉低至低电压。

公开(公告)号：US20110235756A1

公开(公告)日：2011-09-29

申请号：US13151717

申请日：2011-06-02

Applicant: Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Weiqi Ding ,  Sergey Shumarayev ,  Wilson Wong ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H04L27/06

CPC classification number: H04L25/45

Abstract: A loss-of-signal detector includes digital and analog monitoring of incoming data. The incoming signal is compared digitally to at least one predetermined pattern that may indicate a loss of signal, and also is monitored by an analog detector that detects transitions in the data. If the digital comparison fails to match any of the at least one predetermined pattern, or if transitions are detected by the analog monitoring, even if the digital comparison produces a pattern match, then loss of signal is not indicated.

Abstract translation: 信号丢失检测器包括对输入数据进行数字和模拟监测。 输入信号被数字地比较为可以指示信号丢失的至少一个预定模式，并且还由检测数据中的转换的模拟检测器监视。 如果数字比较不能匹配至少一个预定模式中的任何一个，或者如果通过模拟监视检测到转换，即使数字比较产生模式匹配，则不指示信号丢失。

公开(公告)号：US07999588B1

公开(公告)日：2011-08-16

申请号：US12551434

申请日：2009-08-31

Applicant: Mingde Pan ,  Shou-Po Shih ,  Mei Luo ,  Weiqi Ding

Inventor： Mingde Pan ,  Shou-Po Shih ,  Mei Luo ,  Weiqi Ding

IPC: H03K3/017

CPC classification number: H03K5/1565

Abstract: Circuits and a method for tuning an integrated circuit (IC) are disclosed. The IC includes a storage circuit coupled to receive a data signal, a clock input signal and a reset signal. The storage circuit may be used to generate a clock signal. The reset signal is supplied by a reset circuit. The reset circuit may include one or more logic gates to generate the reset signal. The reset circuit receives a phase shifted version of the clock input signal and the reset signal is generated based on the phase shifted version of the clock input signal. In one embodiment, the reset signal is a series of pulses generated at specific intervals to shift the output of the storage circuit from logic high level to logic low level.

Abstract translation: 公开了用于调谐集成电路（IC）的电路和方法。 IC包括耦合以接收数据信号，时钟输入信号和复位信号的存储电路。 存储电路可用于产生时钟信号。 复位信号由复位电路提供。 复位电路可以包括一个或多个逻辑门以产生复位信号。 复位电路接收时钟输入信号的相移版本，并且基于时钟输入信号的相移版本产生复位信号。 在一个实施例中，复位信号是以特定间隔产生的一系列脉冲，以将存储电路的输出从逻辑高电平转换到逻辑低电平。

公开(公告)号：US07952423B2

公开(公告)日：2011-05-31

申请号：US12241706

申请日：2008-09-30

Applicant: Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

Inventor： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

IPC: G05F1/10

CPC classification number: G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

Abstract: A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

Abstract translation: 提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。 定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。

公开(公告)号：US07759972B1

公开(公告)日：2010-07-20

申请号：US11981934

申请日：2007-10-31

Applicant: Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

Inventor： Sergey Shumarayev ,  Wilson Wong ,  Weiqi Ding ,  Thungoc M. Tran ,  Tim Tri Hoang

IPC: H01L25/00

CPC classification number: H03K19/177

Abstract: An integrated circuit device such as a programmable logic device (“PLD”) includes a plurality of blocks of legacy circuitry. These legacy blocks leave at least one corner of the device unoccupied by such legacy circuitry. This at least one corner is used for relatively newly developed circuitry so as to simplify and speed the design of relatively new circuitry, to avoid having to significantly redesign any of the legacy circuitry to give the device the capabilities of the new circuitry, etc. The relatively newly developed circuitry may be high-speed serial data signal interface (“HSSI”) circuitry that is capable of operating at serial data rates faster than any legacy HSSI circuitry on the device.

Abstract translation: 诸如可编程逻辑器件（“PLD”）的集成电路器件包括多个遗留电路块。 这些传统块离开设备的至少一个角落，不被这种遗留电路占用。 这个至少一个角用于相对新开发的电路，以便简化和加速相对新的电路的设计，以避免必须重新设计任何传统电路以给予设备新电路的能力等。 相对新开发的电路可以是高速串行数据信号接口（“HSSI”）电路，其能够以比设备上的任何传统HSSI电路更快的串行数据速率工作。

公开(公告)号：US09429625B1

公开(公告)日：2016-08-30

申请号：US13475256

申请日：2012-05-18

Applicant: Weiqi Ding ,  Sergey Shumarayev

Inventor： Weiqi Ding ,  Sergey Shumarayev

IPC: G01R31/00 ,  G01R31/319 ,  G01R31/40

CPC classification number: G01R31/31924 ,  G01R31/3167 ,  G01R31/40

Abstract: An analog test network includes a conductor. The conductor is coupled to provide a first analog signal from a circuit under test to an analog-to-digital converter circuit. The analog-to-digital converter circuit is operable to generate a first digital signal based on the first analog signal. A control circuit is operable to generate a second digital signal based on the first digital signal. A digital-to-analog converter circuit is operable to generate a second analog signal based on the second digital signal. The conductor is coupled to provide the second analog signal from the digital-to-analog converter circuit to the circuit under test.

Abstract translation: 模拟测试网络包括导体。 导体被耦合以从被测电路提供到模拟 - 数字转换器电路的第一模拟信号。 模数转换器电路可操作以基于第一模拟信号产生第一数字信号。 控制电路可操作以基于第一数字信号产生第二数字信号。 数模转换器电路可操作以基于第二数字信号产生第二模拟信号。 导体被耦合以将第二模拟信号从数模转换器电路提供给被测电路。

公开(公告)号：US08933751B1

公开(公告)日：2015-01-13

申请号：US13475678

申请日：2012-05-18

Applicant: Wilson Wong ,  Weiqi Ding ,  Shuxian Chen ,  Simardeep Maangat ,  Albert Ratnakumar

Inventor： Wilson Wong ,  Weiqi Ding ,  Shuxian Chen ,  Simardeep Maangat ,  Albert Ratnakumar

IPC: H03F3/45 ,  H01G4/40 ,  H03F1/56

CPC classification number: H01G4/40 ,  H01G17/00 ,  H03F1/56

Abstract: A first trimming capacitor having a first terminal and a second terminal is coupled in parallel between a first terminal and a second terminal of a first capacitor. The first trimming capacitor comprises a first plurality of switched capacitors having different capacitances coupled in parallel. Each of the switched capacitors comprises a switch capacitor and a switch coupled in series. In an illustrative application the first capacitor and the first trimming capacitor are coupled between an output terminal of an operational amplifier (op-amp) and an inverting input terminal of the op-amp. A second capacitor and a second trimming capacitor similar to the first capacitor and the first trimming capacitor are coupled between an input and the inverting input terminal of the op-amp.

Abstract translation: 具有第一端子和第二端子的第一微调电容器并联耦合在第一电容器的第一端子和第二端子之间。 第一微调电容器包括具有并联耦合的不同电容的第一多个开关电容器。 每个开关电容器包括开关电容器和串联耦合的开关。 在说明性应用中，第一电容器和第一微调电容器耦合在运算放大器（运算放大器）的输出端和运算放大器的反相输入端之间。 类似于第一电容器和第一微调电容器的第二电容器和第二微调电容器耦合在运算放大器的输入端和反相输入端子之间。

公开(公告)号：US08723572B1

公开(公告)日：2014-05-13

申请号：US13436385

申请日：2012-03-30

Applicant: Weiqi Ding ,  Sergey Shumarayev

Inventor： Weiqi Ding ,  Sergey Shumarayev

IPC: H03K5/12

CPC classification number: H03K5/1565

Abstract: One embodiment relates a method of correcting skew and/or duty cycle distortion in a differential signal using a transmitter buffer circuit. Skew and/or duty cycle distortion may be detected in the differential signal. Delay times for at least two variable-delay buffer circuits are adjusted. The variable-delay buffer circuits may have outputs coupled to control gates of pull-up and pull-down transistors coupled to one or more output nodes of the transmitter buffer circuit. Other embodiments, aspects, and features are also disclosed.

Abstract translation: 一个实施例涉及使用发射机缓冲电路来校正差分信号中的偏移和/或占空比失真的方法。 可以在差分信号中检测到偏斜和/或占空比失真。 调整至少两个可变延迟缓冲电路的延迟时间。 可变延迟缓冲电路可以具有耦合到耦合到发送器缓冲电路的一个或多个输出节点的上拉和下拉晶体管的控制栅极的输出。 还公开了其它实施例，方面和特征。

公开(公告)号：US08705602B1

公开(公告)日：2014-04-22

申请号：US12580587

申请日：2009-10-16

Applicant: Weiqi Ding ,  Mengchi Liu ,  Mingde Pan ,  Thungoc M. Tran ,  Sergey Shumarayev

Inventor： Weiqi Ding ,  Mengchi Liu ,  Mingde Pan ,  Thungoc M. Tran ,  Sergey Shumarayev

IPC: H03H7/30 ,  H03H7/40

CPC classification number: H04L25/03038 ,  H04L25/03343

Abstract: Transmitter equalizer circuitry, e.g., for a serial, digital, data signal, includes tapped delay line circuitry for outputting a plurality of differently delayed versions of the signal propagating through the delay line circuitry. The equalizer circuitry also includes a plurality of electrical current digital-to-analog converters (“DACs”). The equalizer circuitry still further includes controllable (e.g., programmable) routing circuitry for selectably routing the delayed versions of the signal to the various DACs. The current strengths employed by the various DACs are also preferably controllable (e.g., programmable).

Abstract translation: 例如，用于串行数字数据信号的发射机均衡器电路包括用于输出通过延迟线电路传播的信号的多个不同延迟版本的抽头延迟线电路。 均衡器电路还包括多个电流数模转换器（“DAC”）。 均衡器电路还包括可控（例如，可编程）路由电路，用于可选地将信号的延迟版本路由到各​​种DAC。 各种DAC所使用的电流强度也优选是可控的（例如，可编程的）。

公开(公告)号：US08611403B1

公开(公告)日：2013-12-17

申请号：US13446543

申请日：2012-04-13

Applicant: Weiqi Ding

Inventor： Weiqi Ding

IPC: H04B1/38

CPC classification number: G06F1/3206

Abstract: Disclosed are apparatus and methods to advantageously manage transceiver power in an automated manner using adaptation logic that may be implemented on a same integrated circuit as the transceiver circuitry. In one embodiment, a power-consuming component of the transceiver is turned on at a lowest power setting. A determination is made as to whether a first set of eye opening data for a serial data signal meets preset criteria. If the preset criteria are not met by the first set of eye opening data, then the power-consuming component is changed to a second lowest power setting. Another embodiment relates to an integrated circuit including a receiver buffer, a receiver equalization circuit, an eye viewer circuit and adaptation logic. The adaptation logic is configured to obtain the eye opening data and to adapt the receiver equalization circuit to conserve power used. Other embodiments, aspects and features are also disclosed.

Abstract translation: 公开了利用可以在与收发器电路相同的集成电路上实施的自适应逻辑来以自动方式来管理收发器功率的装置和方法。 在一个实施例中，收发器的功耗部件在最低功率设置下被接通。 确定串行数据信号的第一组眼图数据是否满足预设标准。 如果第一组睁眼数据不满足预设标准，则将功耗组件改变为第二低功率设置。 另一个实施例涉及一种集成电路，其包括接收缓冲器，接收器均衡电路，眼睛观察器电路和适配逻辑。 适配逻辑被配置为获得睁眼数据并使接收机均衡电路适应以节省所使用的功率。 还公开了其它实施例，方面和特征。