公开(公告)号：US08611138B1

公开(公告)日：2013-12-17

申请号：US13354740

申请日：2012-01-20

申请人： Charles Y. Chu ,  Jeffrey Xiaoqi Tung

发明人： Charles Y. Chu ,  Jeffrey Xiaoqi Tung

IPC分类号： G11C11/00 ,  G11C17/00 ,  G11C17/18

CPC分类号： G11C17/146 ,  G11C17/16 ,  G11C17/18

摘要： Circuits and techniques for operating a memory cell on an integrated circuit (IC) are disclosed. A disclosed memory cell includes a first inverter coupled to a second inverter to form a first connection and a second connection. The first connection is operable to receive at least a first data signal at a first voltage and the second connection is operable to receive at least a second data signal at a second voltage. A first oxide capacitor and a second oxide capacitor are coupled to the first and second connections respectively. Both the first and second oxide capacitors are coupled to receive a programming signal at a third voltage that may be operable to rupture either one of the first or second oxide capacitor.

摘要翻译： 公开了用于操作集成电路（IC）上的存储单元的电路和技术。 所公开的存储单元包括耦合到第二反相器以形成第一连接和第二连接的第一反相器。 第一连接可操作以在第一电压下接收至少第一数据信号，并且第二连接可操作以在第二电压下接收至少第二数据信号。 第一氧化物电容器和第二氧化物电容器分别耦合到第一和第二连接。 第一和第二氧化物电容器都被耦合以在第三电压处接收编程信号，该第三电压可操作以破坏第一或第二氧化物电容器中的任一个。

公开(公告)号：US08482963B1

公开(公告)日：2013-07-09

申请号：US12629831

申请日：2009-12-02

申请人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

发明人： Jun Liu ,  Yanzhong Xu ,  Shankar Sinha ,  Shih-Lin S. Lee ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar ,  Qi Xiang ,  Irfan Rahim ,  Andy L. Lee ,  Jeffrey T. Watt ,  Srinivas Perisetty

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： Asymmetric transistors may be formed by creating pocket implants on one source-drain terminal of a transistor and not the other. Asymmetric transistors may also be formed using dual-gate structures having first and second gate conductors of different work functions. Stacked transistors may be formed by stacking two transistors of the same channel type in series. One of the source-drain terminals of each of the two transistors is connected to a common node. The gates of the two transistors are also connected together. The two transistors may have different threshold voltages. The threshold voltage of the transistor that is located higher in the stacked transistor may be provided with a lower threshold voltage than the other transistor in the stacked transistor. Stacked transistors may be used to reduce leakage currents in circuits such as memory cells. Asymmetric transistors may also be used in memory cells to reduce leakage.

摘要翻译： 不对称晶体管可以通过在晶体管的一个源极 - 漏极端子上而不是另一个产生凹穴注入来形成。 也可以使用具有不同功函数的第一和第二栅极导体的双栅结构来形成非对称晶体管。 可以通过堆叠相同通道类型的两个晶体管串联形成堆叠晶体管。 两个晶体管中的每一个的源极 - 漏极端子之一连接到公共节点。 两个晶体管的栅极也连接在一起。 两个晶体管可以具有不同的阈值电压。 位于堆叠晶体管中较高的晶体管的阈值电压可以具有比堆叠晶体管中的另一个晶体管更低的阈值电压。 堆叠的晶体管可用于减少诸如存储器单元的电路中的漏电流。 不对称晶体管也可用于存储器单元中以减少泄漏。

公开(公告)号：US07952423B2

公开(公告)日：2011-05-31

申请号：US12241706

申请日：2008-09-30

申请人： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

发明人： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

IPC分类号： G05F1/10

CPC分类号： G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

摘要翻译： 提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。 定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。

公开(公告)号：US08735983B2

公开(公告)日：2014-05-27

申请号：US12324791

申请日：2008-11-26

申请人： Jun Liu ,  Albert Ratnakumar ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

发明人： Jun Liu ,  Albert Ratnakumar ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

IPC分类号： H01L21/02 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/28 ,  H01L29/49

CPC分类号： H01L21/823842 ,  H01L21/28 ,  H01L21/28061 ,  H01L29/49 ,  H01L29/4983 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/7833

摘要： Metal-oxide-semiconductor transistors are provided. A metal-oxide-semiconductor transistor may be formed on a semiconductor substrate. Source and drain regions may be formed in the substrate. A gate insulator such as a high-K dielectric may be formed between the source and drain regions. A gate may be formed from multiple gate conductors. The gate conductors may be metals with different workfunctions. A first of the gate conductors may form a pair of edge gate conductors that are adjacent to dielectric spacers. An opening between the edge gate conductors may be filled with the second gate conductor to form a center gate conductor. A self-aligned gate formation process may be used in fabricating the metal-oxide-semiconductor transistor.

摘要翻译： 提供了金属氧化物半导体晶体管。 可以在半导体衬底上形成金属氧化物半导体晶体管。 源极和漏极区可以形成在衬底中。 可以在源极和漏极区域之间形成诸如高K电介质的栅极绝缘体。 栅极可以由多个栅极导体形成。 栅极导体可以是具有不同功函数的金属。 栅极导体中的第一个可以形成与电介质间隔物相邻的一对边缘栅极导体。 边缘栅极导体之间​​的开口可以用第二栅极导体填充以形成中心栅极导体。 可以在制造金属氧化物半导体晶体管中使用自对准栅极形成工艺。

公开(公告)号：US08138791B1

公开(公告)日：2012-03-20

申请号：US12694603

申请日：2010-01-27

申请人： Albert Ratnakumar ,  Jun Liu ,  Jeffrey Xiaoqi Tung ,  Qi Xiang

发明人： Albert Ratnakumar ,  Jun Liu ,  Jeffrey Xiaoqi Tung ,  Qi Xiang

IPC分类号： H03K19/177

CPC分类号： H03K19/0008 ,  H01L27/11807 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7847 ,  H01L29/7848

摘要： Integrated circuits with stressed transistors are provided. Stressing transistors may increase transistor threshold voltage without the need to increase channel doping. Stressing transistors may reduce total leakage currents. It may be desirable to compressively stress N-channel metal-oxide-semiconductor (NMOS) transistors and tensilely stress P-channel metal-oxide-semiconductor (PMOS) transistors to reduce leakage currents. Techniques that can be used to alter the amount of stressed experienced by transistors may include forming a stress-inducing layer, forming a stress liner, forming diffusion active regions using silicon germanium, silicon carbon, or standard silicon, implementing transistors in single-finger instead of multi-finger configurations, and implanting particles. Any combination of these techniques may be used to provide appropriate amounts of stress to increase the performance or decrease the total leakage current of a transistor.

摘要翻译： 提供了具有应力晶体管的集成电路。 应力晶体管可以增加晶体管阈值电压，而不需要增加沟道掺杂。 应力晶体管可能会减少总漏电流。 可能需要压缩应力N沟道金属氧化物半导体（NMOS）晶体管和拉伸应力P沟道金属氧化物半导体（PMOS）晶体管以减少漏电流。 可用于改变晶体管经受的应力的技术可包括形成应力诱导层，形成应力衬垫，使用硅锗，硅碳或标准硅形成扩散有源区，以单指代替晶体管 的多指配置和植入颗粒。 可以使用这些技术的任何组合来提供适当量的应力以增加晶体管的性能或降低总泄漏电流。

公开(公告)号：US08081502B1

公开(公告)日：2011-12-20

申请号：US12345560

申请日：2008-12-29

申请人： Irfan Rahim ,  Jun Liu ,  Andy L. Lee ,  William Bradley Vest ,  Lu Zhou ,  Qi Xiang ,  Yanzhong Yu ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar

发明人： Irfan Rahim ,  Jun Liu ,  Andy L. Lee ,  William Bradley Vest ,  Lu Zhou ,  Qi Xiang ,  Yanzhong Yu ,  Jeffrey Xiaoqi Tung ,  Albert Ratnakumar

IPC分类号： G11C11/00

CPC分类号： G11C11/412

摘要： An integrated circuit with memory elements is provided. The memory elements may have memory element transistors with body terminals. Body bias control circuitry may supply body bias voltages that strengthen or weaken memory element transistors to improve read and write margins. The body bias control circuitry may dynamically control body bias voltages so that time-varying body bias voltages are supplied to memory element transistors. Address transistors and latch transistors in the memory elements may be selectively strengthened and weakened. Process variations may be compensated by weakening fast transistors and strengthening slow transistors with body bias adjustments.

摘要翻译： 提供了一种具有存储元件的集成电路。 存储器元件可以具有带有主体端子的存储器元件晶体管。 体偏置控制电路可以提供加强或削弱存储元件晶体管的体偏置电压，以改善读和写余量。 体偏置控制电路可以动态地控制体偏置电压，从而将时变体偏置电压提供给存储元件晶体管。 存储元件中的地址晶体管和锁存晶体管可以被选择性地加强和削弱。 过程变化可以通过削弱快速晶体管和加强具有体偏置调整的慢晶体管来补偿。

公开(公告)号：US20100127331A1

公开(公告)日：2010-05-27

申请号：US12324789

申请日：2008-11-26

申请人： Albert Ratnakumar ,  Jun Liu ,  Jeffrey Xiaoqi Tung ,  Qi Xiang

发明人： Albert Ratnakumar ,  Jun Liu ,  Jeffrey Xiaoqi Tung ,  Qi Xiang

IPC分类号： H01L29/78 ,  G06F17/50

CPC分类号： G06F17/5063 ,  H01L29/4983 ,  H01L29/66545 ,  H01L29/78

摘要： Mixed gate metal-oxide-semiconductor transistors are provided. The transistors may have an asymmetric configuration that exhibits increased output resistance. Each transistor may be formed from a gate insulating layer formed on a semiconductor. The gate insulating layer may be a high-K material. Source and drain regions in the semiconductor may define a transistor gate length. The gate length may be larger than the minimum specified by semiconductor fabrication design rules. The transistor gate may be formed from first and second gate conductors with different work functions. The relative sizes of the first and gate conductors in a given transistor control the threshold voltage for the transistor. A computer-aided design tool may be used to receive a circuit design from a user. The tool may generate fabrication masks for the given design that include mixed gate transistors with threshold voltages optimized to meet circuit design criteria.

摘要翻译： 提供混合栅极金属氧化物半导体晶体管。 晶体管可以具有表现出增加的输出电阻的非对称配置。 每个晶体管可以由形成在半导体上的栅极绝缘层形成。 栅极绝缘层可以是高K材料。 半导体中的源极和漏极区域可以限定晶体管栅极长度。 栅极长度可以大于由半导体制造设计规则规定的最小值。 晶体管栅极可以由具有不同功函数的第一和第二栅极导体形成。 给定晶体管中的第一和栅极导体的相对尺寸控制晶体管的阈值电压。 计算机辅助设计工具可用于从用户接收电路设计。 该工具可以为给定的设计生成包括混合栅极晶体管的制造掩模，其具有优化的阈值电压以满足电路设计标准。

公开(公告)号：US20100079200A1

公开(公告)日：2010-04-01

申请号：US12241706

申请日：2008-09-30

申请人： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

发明人： Qi Xiang ,  Albert Ratnakumar ,  Jeffrey Xiaoqi Tung ,  Weiqi Ding

IPC分类号： G05F1/10 ,  H01L21/336

CPC分类号： G05F3/205 ,  H01L29/1083 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for improving analog circuits performance using a circuit design using forward bias and a modified mixed-signal process is presented. A circuit consisting plurality of NMOS and PMOS transistors is defined. The body terminal of the NMOS transistors are coupled to a first voltage source and the body terminal of the PMOS transistors are coupled a second voltage source. Transistors in the circuit are selectively biased by applying the first voltage source to the body terminal of each selected NMOS transistor and applying the second voltage source to the body terminal of each selected PMOS transistor. In one embodiment, the first voltage source and the second voltage source are modifiable to provide forward and reverse bias to the body terminal of the transistors.

摘要翻译： 提出了使用正向偏置电路设计和改进的混合信号处理来提高模拟电路性能的方法。 定义了包括多个NMOS和PMOS晶体管的电路。 NMOS晶体管的主体端子耦合到第一电压源，并且PMOS晶体管的主体端子耦合第二电压源。 通过将第一电压源施加到每个选定的NMOS晶体管的主体端子并将第二电压源施加到每个选择的PMOS晶体管的主体端子来选择性地偏置电路中的晶体管。 在一个实施例中，第一电压源和第二电压源是可修改的，以向晶体管的主体端子提供正向和反向偏置。

公开(公告)号：US08835265B1

公开(公告)日：2014-09-16

申请号：US13525864

申请日：2012-06-18

申请人： Che Ta Hsu ,  Fangyun Richter ,  Ning Cheng ,  Jeffrey Xiaoqi Tung

发明人： Che Ta Hsu ,  Fangyun Richter ,  Ning Cheng ,  Jeffrey Xiaoqi Tung

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L21/8232 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/7833 ,  H01L21/02115 ,  H01L21/02126 ,  H01L21/0217 ,  H01L21/31111 ,  H01L21/8232 ,  H01L21/8238 ,  H01L21/823857 ,  H01L27/092 ,  H01L29/401 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/66583

摘要： An insulating layer is formed on a semiconductor substrate; and holes are patterned in the insulating layer where transistor gates are to be formed. A hard mask spacer layer is formed on the upper surface of the insulating layer and the holes. Next, the spacer layer is anisotropically etched to remove the portion of the spacer layer exposed at the bottom of each hole as well as the portion of the spacer layer on the upper surface of the insulating layer. However, the etching process does not remove all of the portion of the spacer layer formed on the substantially vertical sidewalls of the holes. A high-k dielectric layer is then formed on the remaining vertical portion of the spacer layer and on the exposed upper surfaces of the substrate and the insulating layer. A metal layer is then formed on the high-k dielectric layer; and individual gate structures are completed.

摘要翻译： 绝缘层形成在半导体衬底上; 并且在要形成晶体管栅极的绝缘层中构图孔。 在绝缘层的上表面和孔上形成硬掩模间隔层。 接下来，间隔层被各向异性蚀刻以去除在每个孔的底部暴露的间隔层的部分以及绝缘层的上表面上的间隔层的部分。 然而，蚀刻工艺不会去除在孔的基本上垂直的侧壁上形成的间隔层的所有部分。 然后在间隔层的剩余垂直部分和暴露的基板和绝缘层的上表面上形成高k电介质层。 然后在高k电介质层上形成金属层; 并完成各个门结构。

公开(公告)号：US08242581B1

公开(公告)日：2012-08-14

申请号：US12324793

申请日：2008-11-26

申请人： Albert Ratnakumar ,  Wilson Wong ,  Jun Liu ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

发明人： Albert Ratnakumar ,  Wilson Wong ,  Jun Liu ,  Qi Xiang ,  Jeffrey Xiaoqi Tung

IPC分类号： H01L29/93

CPC分类号： H01L29/94 ,  H01L29/4983 ,  H01L29/93

摘要： Mixed gate varactors are provided. The mixed gate varactors may include a semiconductor region of a given doping type. A first terminal for the varactor may be formed from a gate structure on the semiconductor region. A second terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has the same doping type as the given doping type. A third terminal for the varactor may be formed from a heavily doped region in the semiconductor region that has a different doping type than the given doping type. The gate structure may include multiple gate conductors on a gate insulator. The gate insulator may be a high-K dielectric. The gate conductors may be metals or other materials that have different work functions. A conductive layer such as a layer of polysilicon may electrically connect the first and second gate conductors.

摘要翻译： 提供混合栅极变容二极管。 混合栅极变容二极管可以包括给定掺杂型的半导体区域。 用于变容二极管的第一端可以由半导体区域上的栅极结构形成。 用于变容二极管的第二端子可以由具有与给定掺杂类型相同的掺杂类型的半导体区域中的重掺杂区域形成。 用于变容二极管的第三端子可以由具有与给定掺杂类型不同的掺杂类型的半导体区域中的重掺杂区域形成。 栅极结构可以包括栅极绝缘体上的多个栅极导体。 栅极绝缘体可以是高K电介质。 栅极导体可以是具有不同功函数的金属或其它材料。 诸如多晶硅层的导电层可电连接第一和第二栅极导体。