Hardware security accelerator
    23.
    发明授权

    公开(公告)号:US10708241B1

    公开(公告)日:2020-07-07

    申请号:US16275824

    申请日:2019-02-14

    Abstract: A hardware security accelerator includes a configurable parser that is configured to receive a packet and to extract from the packet headers associated with a set of protocols. The security accelerator also includes a packet type detection unit to determine a type of the packet in response to the set of protocols and to generate a packet type identifier indicative of the type of the packet. A configurable security unit includes a configuration unit and a configurable security engine. The configuration unit configures the configurable security engine according to the type of the packet and to content of at least one of the headers extracted from the packet. The configurable security engine performs security processing of the packet to provide at least one security result.

    CONFIGURABLE LOGIC PLATFORM
    24.
    发明申请

    公开(公告)号:US20190258597A1

    公开(公告)日:2019-08-22

    申请号:US16287986

    申请日:2019-02-27

    Abstract: The following description is directed to a configurable logic platform. In one example, a configurable logic platform includes host logic and a reconfigurable logic region. The reconfigurable logic region can include logic blocks that are configurable to implement application logic. The host logic can be used for encapsulating the reconfigurable logic region. The host logic can include a host interface for communicating with a processor. The host logic can include a management function accessible via the host interface. The management function can be adapted to cause the reconfigurable logic region to be configured with the application logic in response to an authorized request from the host interface. The host logic can include a data path function accessible via the host interface. The data path function can include a layer for formatting data transfers between the host interface and the application logic.

    Generic data integrity check
    25.
    发明授权

    公开(公告)号:US10320956B2

    公开(公告)日:2019-06-11

    申请号:US14594137

    申请日:2015-01-11

    Abstract: A system, comprising: a configurable parser that comprises one or more configurable parsing engines, wherein the configurable parser is arranged to receive a packet and to extract from the packet headers associated with a set of protocols that comprises at least one protocol; a packet type detection unit that is arranged to determine a type of the packet in response to the set of protocols; and a configurable data integrity unit that comprises a configuration unit and at least one configurable data integrity engine; wherein the configuration unit is arranged to configure the at least one configurable data integrity engine according to the set of protocols; and wherein the at least one configurable data integrity engine is arranged to perform data integrity processing of the packet to provide at least one data integrity result.

    Controlling shared resources and context data

    公开(公告)号:US10228869B1

    公开(公告)日:2019-03-12

    申请号:US15716010

    申请日:2017-09-26

    Abstract: Techniques for controlling access to shared resources may include receiving multiple requests to access shared information associated with an identifier. For each of the requests, an entry in a linked list can be allocated to the request, and each entry can be associated with the identifier. The shared information associated with the identifier can be retrieved, and stored in each entry associated with the identifier. A conflict indicator is set in each entry to indicate whether the shared information is available for the request corresponding to the entry. The shared information stored in each entry is provided for each request after the conflict indicator in the corresponding entry indicates the shared information is available for the request.

    Cache index mapping
    27.
    发明授权

    公开(公告)号:US10177795B1

    公开(公告)日:2019-01-08

    申请号:US15394635

    申请日:2016-12-29

    Abstract: Systems and methods in accordance with various embodiments of the present disclosure provide approaches for mapping entries to a cache using a function, such as cyclic redundancy check (CRC). The function can calculate a colored cache index based on a main memory address. The function may cause consecutive address cache indexes to be spread throughout the cache according to the indexes calculated by the function. In some embodiments, each data context may be associated with a different function, enabling different types of packets to be processed while sharing the same cache, reducing evictions of other data contexts and improving performance. Various embodiments can identify a type of packet as the packet is received, and lookup a mapping function based on the type of packet. The function can then be used to lookup the corresponding data context for the packet from the cache, for processing the packet.

    Network traffic load balancing using rotating hash

    公开(公告)号:US10103992B1

    公开(公告)日:2018-10-16

    申请号:US15194312

    申请日:2016-06-27

    Abstract: Disclosed herein are techniques for classifying input network packets evenly into a plurality of classes. An apparatus includes an input port configured to receive a plurality of network packets. The apparatus also includes processing logic configured to receive the plurality of network packets from the input port and classify each packet of the plurality of network packets. For each packet, whether a condition is met is determined, a most recently used hash operation is selected when the condition is not met or a new hash operation is selected when the condition is met; and the selected hash operation is performed on the packet using at least a portion of the packet as an input value to classify the packet. The most recently used hash operation and the new hash operation are configured to classify packets having the same input value into different classes.

    Reduced-latency packet ciphering
    30.
    发明授权

    公开(公告)号:US09960908B1

    公开(公告)日:2018-05-01

    申请号:US14869673

    申请日:2015-09-29

    CPC classification number: H04L9/0637 H04L9/065 H04L9/0838

    Abstract: A hardware cipher module to cipher a packet. The cipher module includes a key scheduling engine and a ciphering engine. The key scheduling engine is configured to receive a compact key and iteratively generate a set of round keys, including a first round key, based on the compact key and determine, based upon a cipher mode indication and a type of ciphering whether to generate a key-scheduling-done indication after the first round key is generated and before all of the set of round keys are generated or to generate the key-scheduling-done indication after all of the set of round keys is generated. The ciphering engine is configured to begin to cipher the packet with one of the set of round keys as a result of receiving the key schedule done indication.

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