公开(公告)号：US20180026440A1

公开(公告)日：2018-01-25

申请号：US15215938

申请日：2016-07-21

Applicant: ANALOG DEVICES, INC.

Inventor： James Zhao ,  Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H02H9/04

Abstract: High voltage clamps with active activation and activation-release control are provided herein. In certain configurations, a clamp can have scalable operating clamping voltage level and can be used to protect the electrical circuit connected to a power supply of a semiconductor chip from damage from an overstress event, such as electrostatic discharge (ESD) events. The pins of the power supply are actively monitored to detect when an overstress event is present, and the clamp is turned-on in response to detecting the overstress event. A timer is used to shut down the clamp after a time delay from detecting the overstress event, thereby providing a false detection shutdown mechanism that prevents the protection clamp from getting falsely activated and remain in the on-state during normal circuit operation.

公开(公告)号：US20170256534A1

公开(公告)日：2017-09-07

申请号：US15060932

申请日：2016-03-04

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H01L27/02

CPC classification number: H01L27/0285 ,  H01L27/0259 ,  H02H9/04 ,  H02H9/046 ,  H03K17/305

Abstract: Apparatus and methods for transient overstress protection with false condition shutdown are provided herein. In certain configurations, a high-voltage tolerant actively-controlled protection circuit includes a transient overstress detection circuit, a clamp circuit electrically connected between a first node and a second node, a bias circuit that biases the clamp circuit, and a false condition shutdown circuit. The transient overstress detection circuit generates a detection signal indicating whether or not a transient overstress event is detected between the first and second nodes. Additionally, the false condition shutdown circuit generates a false condition shutdown signal based on low pass filtering a voltage difference between the first and second nodes, thereby determining independently whether or not power is present. The bias circuit controls operation of the clamp circuit in an on state or an off state based on the detection signal and the false condition shutdown signal.

公开(公告)号：US09438033B2

公开(公告)日：2016-09-06

申请号：US14084350

申请日：2013-11-19

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H02H9/005

Abstract: Electrostatic discharge (ESD) protection devices can protect electronic circuits. In the context of radio frequency (RF) circuits and the like, the insertion loss of conventional ESD protection devices can be undesirable. The amounts of parasitic capacitances at nodes of devices of an ESD protection device are not necessarily symmetrical, with respect to the substrate. Disclosed are techniques which decrease the parasitic capacitances at signal nodes, which improve the insertion loss characteristics of ESD protection devices.

Abstract translation: 静电放电（ESD）保护装置可以保护电子电路。 在射频（RF）电路等的上下文中，常规ESD保护装置的插入损耗可能是不期望的。 ESD保护器件的器件节点处的寄生电容量不一定对称于衬底。 公开了减少信号节点处的寄生电容的技术，其改善ESD保护装置的插入损耗特性。

公开(公告)号：US09362265B2

公开(公告)日：2016-06-07

申请号：US14593477

申请日：2015-01-09

Applicant: Analog Devices, Inc.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L23/62 ,  H01L27/02 ,  H01L21/8222

CPC classification number: H01L27/0262 ,  H01L21/8222 ,  H01L27/0259

Abstract: Apparatus and methods for precision mixed-signal electronic circuit protection are provided. In one embodiment, an apparatus includes a p-well, an n-well, a poly-active diode structure, a p-type active region, and an n-type active region. The poly-active diode structure is formed over the n-well, the p-type active region is formed in the n-well on a first side of the poly-active diode structure, and the n-type active region is formed along a boundary of the p-well and the n-well on a second side of the poly-active diode structure. During a transient electrical event the apparatus is configured to provide conduction paths through and underneath the poly-active diode structure to facilitate injection of carriers in the n-type active region. The protection device can further include another poly-active diode structure formed over the p-well to further enhance carrier injection into the n-type active region.

Abstract translation: 提供了精密混合信号电子电路保护的装置和方法。 在一个实施例中，一种装置包括p阱，n阱，多有源二极管结构，p型有源区和n型有源区。 多极二极管结构形成在n阱上，p型有源区形成在多功能二极管结构的第一侧上的n阱中，并且n型有源区沿着 在多活性二极管结构的第二侧上的p阱和n阱的边界。 在瞬态电气事件期间，该装置被配置为提供穿过多功能二极管结构之间和之下的导电路径，以便于在n型有源区域中注入载流子。 保护装置还可以包括在p阱上形成的另一个多有源二极管结构，以进一步增强对n型有源区的载流子注入。

公开(公告)号：US09293912B2

公开(公告)日：2016-03-22

申请号：US14024426

申请日：2013-09-11

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H02H9/00 ,  H02H9/04

CPC classification number: H02H9/04 ,  H02H9/046

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit generates a detection signal in response to a transient electrical stress. First and second driver circuits of an integrated circuit, each driver having one or more bipolar junction transistors, activate based on the detection signal and generate activation signals. The one or more bipolar junction transistors of the first and second driver circuits are configured to conduct current substantially laterally across respective base regions. A discharge circuit, having an upper discharge element and a lower discharge element, receives the activation signals and activates to attenuate the transient electrical event.

Abstract translation: 公开了与瞬时电气事件相关的主动检测，定时和保护的装置和方法。 检测电路响应瞬时电应力产生检测信号。 集成电路的第一和第二驱动器电路，具有一个或多个双极结型晶体管的每个驱动器基于检测信号而激活并产生激活信号。 第一和第二驱动器电路的一个或多个双极结型晶体管被配置为基本横向地跨过相应的基极区域传导电流。 具有上放电元件和下放电元件的放电电路接收激活信号并激活以衰减瞬时电事件。

公开(公告)号：US08958187B2

公开(公告)日：2015-02-17

申请号：US13673896

申请日：2012-11-09

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo

IPC: H02H9/00 ,  H02H9/04

CPC classification number: H02H9/041 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Apparatus and methods for active detection, timing, and protection related to transient electrical events are disclosed. A detection circuit can generate a first activation signal in response to a transient electrical stress event across a first node and a second node. A blocking circuit is configured to bias the base of a first driver bipolar transistor to slow down discharge of accumulated base charge of a first driver bipolar transistor, which permits the first driver bipolar transistor to remain activated for a longer period of time than had the base of the first driver bipolar transistor been biased to the same voltage as the emitter of the first bipolar transistor. Shut-off circuitry can be included in some embodiments to prevent a discharge circuit from activating during normal operating conditions.

Abstract translation: 公开了与瞬时电气事件相关的主动检测，定时和保护的装置和方法。 检测电路可以响应于穿过第一节点和第二节点的瞬时电应力事件而产生第一激活信号。 阻塞电路被配置为偏置第一驱动器双极晶体管的基极以减慢第一驱动器双极晶体管的累积基极电荷的放电，这允许第一驱动器双极晶体管保持激活更长的时间段，而不是基极 的第一驱动器双极晶体管被偏置到与第一双极晶体管的发射极相同的电压。 在一些实施例中可以包括关断电路以防止放电电路在正常操作条件下激活。

公开(公告)号：US08878344B2

公开(公告)日：2014-11-04

申请号：US13655026

申请日：2012-10-18

Applicant: Analog Devices, Inc.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Shuyun Zhang

IPC: H01L29/66

CPC classification number: H01L29/735 ,  H01L29/20 ,  H01L29/6631

Abstract: Compound semiconductor lateral PNP bipolar transistors are fabricated based on processes traditionally used for formation of compound semiconductor NPN heterojunction bipolar transistors and hence such PNP bipolar transistors can be fabricated inexpensively using existing fabrication technologies. In particular, GaAs-based lateral PNP bipolar transistors are fabricated using GaAs-based NPN heterojunction bipolar transistor fabrication processes.

Abstract translation: 基于传统上用于形成化合物半导体NPN异质结双极晶体管的工艺制造复合半导体横向PNP双极晶体管，因此可以使用现有的制造技术廉价地制造这种PNP双极晶体管。 特别地，基于GaAs的NPN异质结双极晶体管制造工艺制造了基于GaAs的横向PNP双极晶体管。

公开(公告)号：US20140084331A1

公开(公告)日：2014-03-27

申请号：US13625611

申请日：2012-09-24

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Shuyun Zhang

IPC: H01L29/747 ,  H01L21/332

CPC classification number: H01L21/8252 ,  H01L27/0248 ,  H01L27/0605 ,  H01L29/41758 ,  H01L29/42316 ,  H01L29/7783

Abstract: A protection clamp is provided between a first terminal and a second terminal, and includes a multi-gate high electron mobility transistor (HEMT), a current limiting circuit, and a forward trigger control circuit. The multi-gate HEMT includes a drain/source, a source/drain, a first depletion-mode (D-mode) gate, a second D-mode gate, and an enhancement-mode (E-mode) gate disposed between the first and second D-mode gates. The drain/source and the first D-mode gate are connected to the first terminal and the source/drain and the second D-mode gate are connected to the second terminal. The forward trigger control and the current limiting circuits are coupled between the E-mode gate and the first and second terminals, respectively. The forward trigger control circuit provides an activation voltage to the E-mode gate when a voltage of the first terminal exceeds a voltage of the second terminal by a forward trigger voltage.

Abstract translation: 在第一端子和第二端子之间提供保护夹，并且包括多门高电子迁移率晶体管（HEMT），限流电路和正向触发控制电路。 多栅极HEMT包括漏极/源极，源极/漏极，第一耗尽模式（D模式）栅极，第二D模式栅极和设置在第一和第二栅极之间的增强模式（E模式）栅极 和第二D模式门。 漏极/源极和第一D型栅极连接到第一端子，源极/漏极和第二D型栅极连接到第二端子。 正向触发控制和限流电路分别耦合在E模式门和第一和第二端子之间。 当第一端子的电压通过正向触发电压超过第二端子的电压时，正向触发控制电路向E模式栅极提供激活电压。

公开(公告)号：US11764204B2

公开(公告)日：2023-09-19

申请号：US16905687

申请日：2020-06-18

Applicant: Analog Devices, Inc.

Inventor： Ralph D. Moore ,  Franklin M. Murden ,  Peter Delos ,  Srivatsan Parthasarathy ,  Javier Salcedo ,  John Guido

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0248 ,  H02H9/046

Abstract: Herein disclosed are systems and circuitry for protecting against overdrive and electrostatic discharge. For example, protection circuitry may include field effect transistors to discharge overdrive outside of an operational voltage range of a circuit in some embodiments to prevent damage to the circuit. Further, the protection circuitry may utilize diode features inherent in the field effect transistors to protect against electrostatic discharge in some embodiments. The circuitry may be implemented in radio frequency sampling analog-to-digital converters and can provide for single-ended signal input and/or output for the analog-to-digital converters.

公开(公告)号：US10861845B2

公开(公告)日：2020-12-08

申请号：US15370912

申请日：2016-12-06

Applicant: ANALOG DEVICES, INC.

Inventor： Javier Alejandro Salcedo ,  Srivatsan Parthasarathy

IPC: H01L27/02 ,  H02H9/04

Abstract: In certain configurations, an input/output (IO) interface of a semiconductor chip includes a pin, an interface switch connected to the pin, and an overstress detection and active control circuit that controls a resistance of the interface switch with active feedback. The overstress detection and active control circuit increases a resistance of the interface switch in response to detection of a transient overstress event between a first node and a second node. Accordingly, the overstress detection and active control circuit provides separate detection and logic control to selectively modify the resistance of the interface switch such that the interface switch operates with low resistance during normal operating conditions and with high resistance during overstress conditions.