公开(公告)号：US09954356B2

公开(公告)日：2018-04-24

申请号：US14797675

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04 ,  H02H9/02 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an ESD protection circuit includes two or more pairs of field effect transistors (FETs) electrically connected in series between a radio frequency signal pin and a radio frequency ground pin. Each of the two or more pairs of FETs includes a negative ESD protection FET for providing protection from negative polarity ESD events and a positive ESD protection FET for providing protection from positive polarity ESD events. The source and gate of the negative ESD protection FET are electrically connected to one another, and the source and gate of the positive ESD protection FET are electrically connected to one another. Additionally, the drains of the negative and positive ESD protection FETs are electrically connected to one another. The ESD protection circuit exhibits a relatively low capacitance and flat capacitance versus voltage characteristic.

公开(公告)号：US09431320B2

公开(公告)日：2016-08-30

申请号：US14021894

申请日：2013-09-09

Applicant: ANALOG DEVICES, INC.

Inventor： Rodrigo Carrillo-Ramirez

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/00014

Abstract: In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality of openings. The metal pads are vertically aligned and the placement of the openings in each metal pad is such that the openings are laterally offset and substantially do not directly overlie or underlie one another. As seen in a top-down view, the through-silicon via etch may “see” a metal etch stop that extends continuously across the width of the via, although different portions of the etch stop may be distributed on different vertical levels due to the presence of openings in the metal pads. The openings in the metal pads facilitate integrated circuit fabrication their respective levels and the aggregate structure formed by the metal pads provides an effective etch stop for the through-silicon via etch.

Abstract translation: 在一些实施方案中，用于捕获或与硅通孔连接的金属焊盘具有穿过其的多个开口。 上层的另一金属垫也可包括多个开口。 金属焊盘是垂直对准的，并且每个金属焊盘中的开口的放置使得开口横向偏移并且基本上不直接覆盖在彼此之上或之下。 如从俯视图中看到的那样，贯穿硅通孔蚀刻可以“看到”金属蚀刻停止件，其连续延伸穿过通孔的宽度，尽管蚀刻停止件的不同部分可以分布在不同的垂直水平面上， 在金属垫中存在开口。 金属焊盘中的开口有助于集成电路制造它们各自的电平，并且由金属焊盘形成的聚集结构为穿通硅通孔蚀刻提供有效的蚀刻停止。

公开(公告)号：US09438033B2

公开(公告)日：2016-09-06

申请号：US14084350

申请日：2013-11-19

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/00 ,  H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H02H9/005

Abstract: Electrostatic discharge (ESD) protection devices can protect electronic circuits. In the context of radio frequency (RF) circuits and the like, the insertion loss of conventional ESD protection devices can be undesirable. The amounts of parasitic capacitances at nodes of devices of an ESD protection device are not necessarily symmetrical, with respect to the substrate. Disclosed are techniques which decrease the parasitic capacitances at signal nodes, which improve the insertion loss characteristics of ESD protection devices.

Abstract translation: 静电放电（ESD）保护装置可以保护电子电路。 在射频（RF）电路等的上下文中，常规ESD保护装置的插入损耗可能是不期望的。 ESD保护器件的器件节点处的寄生电容量不一定对称于衬底。 公开了减少信号节点处的寄生电容的技术，其改善ESD保护装置的插入损耗特性。

公开(公告)号：US20140264881A1

公开(公告)日：2014-09-18

申请号：US14021894

申请日：2013-09-09

Applicant: ANALOG DEVICES, INC.

Inventor： Rodrigo Carrillo-Ramirez

IPC: H01L23/48 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L24/03 ,  H01L24/05 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2924/0002 ,  H01L2924/10253 ,  H01L2924/00 ,  H01L2924/00014

Abstract: In some implementations, a metal pad for capturing or interfacing with through-silicon vias has a plurality of openings through it. Another metal pad on an upper level can also include a plurality of openings. The metal pads are vertically aligned and the placement of the openings in each metal pad is such that the openings are laterally offset and substantially do not directly overlie or underlie one another. As seen in a top-down view, the through-silicon via etch may “see” a metal etch stop that extends continuously across the width of the via, although different portions of the etch stop may be distributed on different vertical levels due to the presence of openings in the metal pads. The openings in the metal pads facilitate integrated circuit fabrication their respective levels and the aggregate structure formed by the metal pads provides an effective etch stop for the through-silicon via etch.

Abstract translation: 在一些实施方案中，用于捕获或与硅通孔连接的金属焊盘具有穿过其的多个开口。 上层的另一金属垫也可包括多个开口。 金属焊盘是垂直对准的，并且每个金属焊盘中的开口的放置使得开口横向偏移并且基本上不直接覆盖在彼此之上或之下。 如从俯视图中看到的那样，贯穿硅通孔蚀刻可以“看到”金属蚀刻停止件，其连续延伸穿过通孔的宽度，尽管蚀刻停止件的不同部分可以分布在不同的垂直水平面上， 在金属垫中存在开口。 金属焊盘中的开口有助于集成电路制造它们各自的电平，并且由金属焊盘形成的聚集结构为穿通硅通孔蚀刻提供有效的蚀刻停止。

公开(公告)号：US09831666B2

公开(公告)日：2017-11-28

申请号：US14797770

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.

公开(公告)号：US20160336740A1

公开(公告)日：2016-11-17

申请号：US14797770

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an integrated circuit includes a first pin, a second pin, a forward ESD protection circuit, and a reverse ESD protection circuit. The forward ESD protection circuit includes one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the first pin and the second pin. A first P+/N-EPI diode of the one or more P+/N-EPI diodes includes an anode electrically connected to the first pin. The reverse ESD protection circuit comprising one or more P+/N-EPI diodes, one or more ESD protection devices, and one or more P-EPI/N+ diodes electrically connected in series between the second pin and the first pin. A first P-EPI/N+ diode of the one or more P-EPI/N+ diodes includes a cathode electrically connected to the first pin.

Abstract translation: 提供射频电路的静电放电（ESD）保护装置和方法。 在某些配置中，集成电路包括第一引脚，第二引脚，正向ESD保护电路和反向ESD保护电路。 正向ESD保护电路包括一个或多个P + / N-EPI二极管，一个或多个ESD保护器件以及串联在第一引脚和第二引脚之间电连接的一个或多个P-EPI / N +二极管。 一个或多个P + / N-EPI二极管的第一P + / N-EPI二极管包括电连接到第一引脚的阳极。 反向ESD保护电路包括一个或多个P + / N-EPI二极管，一个或多个ESD保护器件以及串联在第二引脚和第一引脚之间电连接的一个或多个P-EPI / N +二极管。 一个或多个P-EPI / N +二极管的第一P-EPI / N +二极管包括电连接到第一引脚的阴极。

公开(公告)号：US20160190075A1

公开(公告)日：2016-06-30

申请号：US14613005

申请日：2015-02-03

Applicant: ANALOG DEVICES, INC.

Inventor： Andrew Pye ,  Rodrigo Carrillo-Ramirez

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/495

CPC classification number: H01L23/66 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/14215 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01005 ,  H01L2224/05599

Abstract: An integrated circuit can include a group of bond pads alternating between bond pads configured to provide a return path and bond pads configured to provide a signal bond pad. For example, five bond pads can be arranged in a return-signal-return-signal-return arrangement. The integrated circuit can further be configured to receive or transmit high frequency signals.

Abstract translation: 集成电路可以包括在配置成提供返回路径的接合焊盘和被配置为提供信号接合焊盘的接合焊盘之间交替的一组接合焊盘。 例如，可以以返回信号返回信号返回装置布置五个接合焊盘。 集成电路还可以被配置为接收或发送高频信号。

公开(公告)号：US20160336744A1

公开(公告)日：2016-11-17

申请号：US14797675

申请日：2015-07-13

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Javier Alejandro Salcedo ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04

CPC classification number: H02H9/046 ,  H01L27/0248 ,  H01L27/0266 ,  H02H9/04

Abstract: Apparatus and methods for electrostatic discharge (ESD) protection of radio frequency circuits are provided. In certain configurations, an ESD protection circuit includes two or more pairs of field effect transistors (FETs) electrically connected in series between a radio frequency signal pin and a radio frequency ground pin. Each of the two or more pairs of FETs includes a negative ESD protection FET for providing protection from negative polarity ESD events and a positive ESD protection FET for providing protection from positive polarity ESD events. The source and gate of the negative ESD protection FET are electrically connected to one another, and the source and gate of the positive ESD protection FET are electrically connected to one another. Additionally, the drains of the negative and positive ESD protection FETs are electrically connected to one another. The ESD protection circuit exhibits a relatively low capacitance and flat capacitance versus voltage characteristic.

Abstract translation: 提供射频电路的静电放电（ESD）保护装置和方法。 在某些配置中，ESD保护电路包括串联电连接在射频信号引脚和射频接地引脚之间的两对或更多对场效应晶体管（FET）。 两对或更多对FET中的每一个包括用于提供对负极性ESD事件的保护的负ESD保护FET和用于提供对正极性ESD事件的保护的正ESD保护FET。 负ESD保护FET的源极和栅极彼此电连接，并且正ESD保护FET的源极和栅极彼此电连接。 此外，负极和正极ESD保护FET的漏极彼此电连接。 ESD保护电路具有相对低的电容和平坦的电容对电压特性。

公开(公告)号：US09437558B2

公开(公告)日：2016-09-06

申请号：US14613005

申请日：2015-02-03

Applicant: ANALOG DEVICES, INC.

Inventor： Andrew Pye ,  Rodrigo Carrillo-Ramirez

IPC: H01L23/495 ,  H01L23/66 ,  H01L23/00

CPC classification number: H01L23/66 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49575 ,  H01L24/05 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2223/6611 ,  H01L2223/6638 ,  H01L2224/04042 ,  H01L2224/05014 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/1421 ,  H01L2924/14215 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/01005 ,  H01L2224/05599

Abstract: An integrated circuit can include a group of bond pads alternating between bond pads configured to provide a return path and bond pads configured to provide a signal bond pad. For example, five bond pads can be arranged in a return-signal-return-signal-return arrangement. The integrated circuit can further be configured to receive or transmit high frequency signals.

Abstract translation: 集成电路可以包括在配置成提供返回路径的接合焊盘和被配置为提供信号接合焊盘的接合焊盘之间交替的一组接合焊盘。 例如，可以以返回信号返回信号返回装置布置五个接合焊盘。 集成电路还可以被配置为接收或发送高频信号。

公开(公告)号：US20150138678A1

公开(公告)日：2015-05-21

申请号：US14084350

申请日：2013-11-19

Applicant: ANALOG DEVICES, INC.

Inventor： Srivatsan Parthasarathy ,  Rodrigo Carrillo-Ramirez

IPC: H02H9/04 ,  H02H9/00

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H02H9/005

Abstract: Electrostatic discharge (ESD) protection devices can protect electronic circuits. In the context of radio frequency (RF) circuits and the like, the insertion loss of conventional ESD protection devices can be undesirable. The amounts of parasitic capacitances at nodes of devices of an ESD protection device are not necessarily symmetrical, with respect to the substrate. Disclosed are techniques which decrease the parasitic capacitances at signal nodes, which improve the insertion loss characteristics of ESD protection devices.

Abstract translation: 静电放电（ESD）保护装置可以保护电子电路。 在射频（RF）电路等的上下文中，常规ESD保护装置的插入损耗可能是不期望的。 ESD保护器件的器件节点处的寄生电容量不一定对称于衬底。 公开了减少信号节点处的寄生电容的技术，其改善ESD保护装置的插入损耗特性。