公开(公告)号：US20050145944A1

公开(公告)日：2005-07-07

申请号：US10745978

申请日：2003-12-24

申请人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

发明人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC分类号： H01L21/28 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/10 ,  H01L29/49 ,  H01L27/12

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

摘要翻译： 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

公开(公告)号：US07662689B2

公开(公告)日：2010-02-16

申请号：US10747321

申请日：2003-12-23

申请人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

发明人： Boyan Boyanov ,  Anand Murthy ,  Brian S. Doyle ,  Robert Chau

IPC分类号： H01L21/8236

CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

摘要翻译： 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

公开(公告)号：US07642610B2

公开(公告)日：2010-01-05

申请号：US11715703

申请日：2007-03-08

申请人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

发明人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC分类号： H01L21/00

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

摘要翻译： 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

公开(公告)号：US20090315076A1

公开(公告)日：2009-12-24

申请号：US12553033

申请日：2009-09-02

申请人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

发明人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian S. Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

摘要翻译： 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

公开(公告)号：US07427775B2

公开(公告)日：2008-09-23

申请号：US11789338

申请日：2007-04-24

申请人： Anand Murthy ,  Justin K. Brask ,  Andrew N. Westmeyer ,  Boyan Boyanov ,  Nick Lindert

发明人： Anand Murthy ,  Justin K. Brask ,  Andrew N. Westmeyer ,  Boyan Boyanov ,  Nick Lindert

IPC分类号： H01L29/06

CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7848

摘要： The mobility of carriers may be increased in strained channel epitaxial source/drain transistors. Doped silicon material may be blanket deposited after removing ion implanted source/drain regions. The blanket deposition forms amorphous films over non-source/drain areas and crystalline films in source/drain regions. By using an etch which is selective to amorphous silicon, the amorphous material may be removed. This may avoid some problems associated with selective deposition of the doped silicon material.

摘要翻译： 在应变通道外延源/漏极晶体管中，载流子的迁移率可能会增加。 在去除离子注入的源极/漏极区之后，掺杂的硅材料可以被覆盖。 覆盖沉积在非源极/漏极区域和源极/漏极区域中形成晶体膜形成非晶态膜。 通过使用对非晶硅有选择性的蚀刻，可以去除非晶材料。 这可以避免与掺杂硅材料的选择性沉积相关的一些问题。

公开(公告)号：US20070170464A1

公开(公告)日：2007-07-26

申请号：US11715703

申请日：2007-03-08

申请人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

发明人： Anand Murthy ,  Boyan Boyanov ,  Suman Datta ,  Brian Doyle ,  Been-Yih Jin ,  Shaofeng Yu ,  Robert Chau

IPC分类号： H01L31/00

CPC分类号： H01L29/1054 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823857 ,  H01L29/66636 ,  H01L29/7842 ,  H01L29/7848

摘要： Various embodiments of the invention relate to a PMOS device having a transistor channel of silicon germanium material on a substrate, a gate dielectric having a dielectric constant greater than that of silicon dioxide on the channel, a gate electrode conductor material having a work function in a range between a valence energy band edge and a conductor energy band edge for silicon on the gate dielectric, and a gate electrode semiconductor material on the gate electrode conductor material.

摘要翻译： 本发明的各种实施例涉及在衬底上具有硅锗材料的晶体管沟道的PMOS器件，介电常数大于沟道上的二氧化硅的介电常数的栅极电介质，具有功函数的栅电极导体材料 在栅极电介质上的硅的价态能带边缘和导体能带边缘之间的范围，以及栅电极导体材料上的栅电极半导体材料。

公开(公告)号：US06974733B2

公开(公告)日：2005-12-13

申请号：US10463080

申请日：2003-06-16

申请人： Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

发明人： Boyan Boyanov ,  Brian Doyle ,  Jack Kavalieros ,  Anand Murthy ,  Robert Chau

IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/78 ,  H01L21/338

CPC分类号： H01L29/7842 ,  H01L29/1054 ,  H01L29/66666 ,  H01L29/7827

摘要： There is disclosed an apparatus including a straining substrate, a device over the substrate including a channel, wherein the straining substrate strains the device in a direction substantially perpendicular to a direction of current flow in the channel.

摘要翻译： 公开了一种装置，包括应变基片，包括通道的衬底上的器件，其中应变衬底沿着基本上垂直于沟道中的电流方向的方向施加器件。

公开(公告)号：US20050253200A1

公开(公告)日：2005-11-17

申请号：US11171097

申请日：2005-06-29

申请人： Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

发明人： Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L29/06

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

公开(公告)号：US20050136584A1

公开(公告)日：2005-06-23

申请号：US10747321

申请日：2003-12-23

申请人： Boyan Boyanov ,  Anand Murthy ,  Brian Doyle ,  Robert Chau

发明人： Boyan Boyanov ,  Anand Murthy ,  Brian Doyle ,  Robert Chau

IPC分类号： H01L21/20 ,  H01L21/205 ,  H01L31/0328 ,  H01L21/8238

CPC分类号： H01L29/7849 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/0251 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L27/092 ,  H01L29/78

摘要： Various embodiments of the invention relate to a CMOS device having (1) an NMOS channel of silicon material selectively deposited on a first area of a graded silicon germanium substrate such that the selectively deposited silicon material experiences a tensile strain caused by the lattice spacing of the silicon material being smaller than the lattice spacing of the graded silicon germanium substrate material at the first area, and (2) a PMOS channel of silicon germanium material selectively deposited on a second area of the substrate such that the selectively deposited silicon germanium material experiences a compressive strain caused by the lattice spacing of the selectively deposited silicon germanium material being larger than the lattice spacing of the graded silicon germanium substrate material at the second area.

摘要翻译： 本发明的各种实施例涉及一种CMOS器件，其具有（1）选择性地沉积在渐变硅锗衬底的第一区域上的硅材料的NMOS沟道，使得选择性沉积的硅材料经历由晶格间隔引起的拉伸应变 硅材料小于第一区域处的渐变硅锗衬底材料的晶格间距，以及（2）选择性地沉积在衬底的第二区域上的硅锗材料的PMOS沟道，使得选择性沉积的硅锗材料经历 由选择性沉积的硅锗材料的晶格间距引起的压缩应变大于第二区域处的分级硅锗衬底材料的晶格间距。

公开(公告)号：US20050130454A1

公开(公告)日：2005-06-16

申请号：US10731269

申请日：2003-12-08

申请人： Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

发明人： Anand Murthy ,  Boyan Boyanov ,  Glenn Glass ,  Thomas Hoffmann

IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L29/78 ,  H01L21/28

CPC分类号： H01L29/7848 ,  H01L21/28518 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/167 ,  H01L29/36 ,  H01L29/41725 ,  H01L29/6628 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/7842 ,  Y10S438/933

摘要： An embodiment of the invention reduces the external resistance of a transistor by utilizing a silicon germanium alloy for the source and drain regions and a nickel silicon germanium self-aligned silicide (i.e., salicide) layer to form the contact surface of the source and drain regions. The interface of the silicon germanium and the nickel silicon germanium silicide has a lower specific contact resistivity based on a decreased metal-semiconductor work function between the silicon germanium and the silicide and the increased carrier mobility in silicon germanium versus silicon. The silicon germanium may be doped to further tune its electrical properties. A reduction of the external resistance of a transistor equates to increased transistor performance both in switching speed and power consumption.

摘要翻译： 本发明的一个实施例通过利用用于源极和漏极区域的硅锗合金和镍硅锗自对准硅化物（即，自对准硅化物）层来形成源极和漏极区域的接触表面来降低晶体管的外部电阻 。 基于硅锗和硅化物之间的金属半导体功函数降低，硅锗与硅硅锗硅的界面具有较低的比接触电阻率，并且硅锗与硅中的载流子迁移率增加。 可以掺杂硅锗以进一步调整其电性能。 降低晶体管的外部电阻等同于在开关速度和功耗方面提高晶体管的性能。