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    Thyristor semiconductor memory device and method of manufacture
    21.
    发明授权
    Thyristor semiconductor memory device and method of manufacture 失效
    晶闸管半导体存储器件及其制造方法

    公开(公告)号：US06998298B1

    公开(公告)日：2006-02-14

    申请号：US10639058

    申请日：2003-08-11

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： H01L21/332

    CPC分类号： H01L29/7408 ,  H01L29/7436

    摘要： A thyristor memory device may comprise a capacitor electrode formed over a base region of the thyristor using a replacement gate process. During formation of the thyristor, a base-emitter boundary may be aligned relative to a shoulder of the capacitor electrode. In a particular embodiment, the replacement gate process may comprise defining a trench in a layer of dielectric over semiconductor material. Conductive material for the electrode may be formed over the dielectric and in the trench. It may further be patterned to form a shoulder for the electrode that extends over regions of the dielectric over a base region for the thyristor. The extent of the shoulder may be used to pattern the dielectric and/or to assist alignment of implants for the base and emitter regions of the thyristor.

    摘要翻译： 晶闸管存储器件可以包括使用替换栅极工艺在晶闸管的基极区域上形成的电容器电极。 在晶闸管的形成期间，基极 - 发射极边界可以相对于电容器电极的台肩对准。 在特定实施例中，替换栅极工艺可以包括在半导体材料上的介电层中限定沟槽。 用于电极的导电材料可以形成在电介质和沟槽中。 可以进一步图案化以形成电极的肩部，该电极在用于晶闸管的基极区域上的电介质的区域上延伸。 可以使用肩部的程度来图案化电介质和/或辅助晶闸管的基极和发射极区域的植入物的对准。

    Very dense NVM bitcell
    22.
    发明授权
    Very dense NVM bitcell 有权
    非常密集的NVM位单元

    公开(公告)号：US08598642B2

    公开(公告)日：2013-12-03

    申请号：US13027048

    申请日：2011-02-14

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： H01L21/02

    CPC分类号： G11C16/10 ,  G06F17/5068 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7885

    摘要： An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.

    摘要翻译： 描述了非对称非易失性存储器位单元。 位单元包括源极和漏极区域，其包括相同导电类型的载流子。 浮动栅极位于阱的顶部，并且在沟道区域以及源极和漏极区域的至少一部分上延伸。 漏极区域包括具有第二导电类型的附加载体，允许频带带通隧道。 源极区域包括第一导电类型的附加载流子，从而增加源极 - 栅极电容。 因此，位单元集成了选择装置，从而减小了位单元的整体尺寸。 可以在没有任何额外的CMOS工艺步骤的情况下创建位单元，或者通过添加单个额外的掩模步骤来创建位单元。

    Fabricating a gate oxide
    23.
    发明授权
    Fabricating a gate oxide 有权
    制造栅极氧化物

    公开(公告)号：US08501562B1

    公开(公告)日：2013-08-06

    申请号：US12717966

    申请日：2010-03-05

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： H01L21/8242 ,  H01L21/336 ,  H01L21/76

    CPC分类号： H01L21/28273 ,  H01L21/76224 ,  H01L27/11206 ,  H01L29/66825

    摘要： An example of a method of fabricating a gate oxide of a floating gate transistor includes forming a plurality of shallow trench isolation (STI) regions in a silicon wafer. The method also includes selectively filling the STI regions with oxide. Further, the method includes forming sacrificial oxide regions on the silicon wafer. Furthermore, the method includes forming implant regions in the silicon wafer. In addition, the method includes selectively removing the sacrificial oxide regions. The method further includes forming the gate oxide.

    摘要翻译： 制造浮栅晶体管的栅极氧化物的方法的实例包括在硅晶片中形成多个浅沟槽隔离（STI）区域。 该方法还包括用氧化物选择性填充STI区域。 此外，该方法包括在硅晶片上形成牺牲氧化物区域。 此外，该方法包括在硅晶片中形成注入区域。 此外，该方法包括选择性地去除牺牲氧化物区域。 该方法还包括形成栅极氧化物。

    Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor
    24.
    发明申请
    Asymmetric Dense Floating Gate Nonvolatile Memory with Decoupled Capacitor 有权
    具有解耦电容器的不对称密集浮栅非易失性存储器

    公开(公告)号：US20130193501A1

    公开(公告)日：2013-08-01

    申请号：US13361801

    申请日：2012-01-30

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： H01L29/788

    CPC分类号： H01L29/788 ,  G11C16/0408 ,  H01L27/0207 ,  H01L27/11558 ,  H01L29/66825 ,  H01L29/7885

    摘要： A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.

    摘要翻译： 具有一个或多个有源区的非易失性存储器（“NVM”）位单元，其电容耦合到浮置栅极，但是与源极和漏极分离。 从源极和漏极分离的电容器的包含允许改善对浮动栅极的电压的控制。 这反过来允许以比现有的比特单元更高的效率执行CHEI（或IHEI），从而需要电荷泵来向比特单元提供电流，最终减小比特单元的总大小。 比特单元可以成对地构造，进一步减少了每个比特单元的空间要求，从而减轻了单独电容器的空间要求。 位元还可以由CHEI（或IHEI）和BTBT单独操作，具体取决于在源极，漏极和电容/ s上施加的电压。

    Very Dense NVM Bitcell
    25.
    发明申请
    Very Dense NVM Bitcell 有权
    非常密集的NVM Bitcell

    公开(公告)号：US20120205734A1

    公开(公告)日：2012-08-16

    申请号：US13027048

    申请日：2011-02-14

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： H01L29/788 ,  H01L21/336

    CPC分类号： G11C16/10 ,  G06F17/5068 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/788 ,  H01L29/7885

    摘要： An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.

    摘要翻译： 描述了非对称非易失性存储器位单元。 位单元包括源极和漏极区域，其包括相同导电类型的载流子。 浮动栅极位于阱的顶部，并且在沟道区域以及源极和漏极区域的至少一部分上延伸。 漏极区域包括具有第二导电类型的附加载体，允许频带带通隧道。 源极区域包括第一导电类型的附加载流子，从而增加源极 - 栅极电容。 因此，位单元集成了选择装置，从而减小了位单元的整体尺寸。 可以在没有任何额外的CMOS工艺步骤的情况下创建位单元，或者通过添加单个额外的掩模步骤来创建位单元。

    METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES
    26.
    发明申请
    METHOD FOR DEPOSITING A DIELECTRIC ONTO A FLOATING GATE FOR STRAINED SEMICONDUCTOR DEVICES 审中-公开
    将介电沉积到应变半导体器件的浮动栅上的方法

    公开(公告)号：US20120086068A1

    公开(公告)日：2012-04-12

    申请号：US12898737

    申请日：2010-10-06

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： H01L27/092 ,  H01L21/8238

    CPC分类号： H01L29/7881 ,  H01L21/823807 ,  H01L29/66825

    摘要： A method for forming a semiconductor device and a corresponding device are provided. The method includes forming a floating gate device in a process with dual strain layers, and an etch stop layer. An oxide is formed between the floating gate device and a nitride layer above the floating gate.

    摘要翻译： 提供了一种用于形成半导体器件和相应器件的方法。 该方法包括在具有双应变层的工艺中形成浮栅器件，以及蚀刻停止层。 浮置栅极器件与浮栅之上的氮化物层之间形成氧化物。

    Non-volatile memory with programming through band-to-band tunneling and impact ionization gate current
    27.
    发明授权
    Non-volatile memory with programming through band-to-band tunneling and impact ionization gate current 有权
    非易失性存储器，通过带 - 带隧穿和冲击电离栅极电流进行编程

    公开(公告)号：US07474568B2

    公开(公告)日：2009-01-06

    申请号：US11601474

    申请日：2006-11-16

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： G11C11/34

    CPC分类号： G11C16/12

    摘要： Electronic circuitry is described having a first transistor having a first gate dielectric located between an electrically floating gate and a semiconductor substrate. The first injection current flows through the first gate dielectric to establish a first amount of electrical charge on the gate electrode. The electronic circuitry also includes a second transistor having a second gate dielectric located between the gate electrode and the semiconductor substrate. A band-to-band tunneling current flows between valence and conduction bands of the second transistor to create a second injection current that flows through the second gate dielectric to establish the first amount of electrical charge on the gate electrode. Non volatile memory cell circuits having the above described circuitry are also described.

    摘要翻译： 电子电路被描述为具有位于电浮置栅极和半导体衬底之间的第一栅极电介质的第一晶体管。 第一注入电流流过第一栅极电介质以在栅电极上建立第一量的电荷。 电子电路还包括具有位于栅电极和半导体衬底之间的第二栅极电介质的第二晶体管。 带间隧穿电流在第二晶体管的价带和导带之间流动，以产生流过第二栅极电介质的第二注入电流，以在栅电极上建立第一量的电荷。 还描述了具有上述电路的非易失性存储单元电路。

    Non-volatile memory devices having floating-gates fets with different source-gate and drain-gate border lengths
    28.
    发明申请
    Non-volatile memory devices having floating-gates fets with different source-gate and drain-gate border lengths 有权
    具有不同源栅极和漏极边界长度的浮置栅极的非易失性存储器件

    公开(公告)号：US20080186772A1

    公开(公告)日：2008-08-07

    申请号：US11701710

    申请日：2007-02-02

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： G11C11/40 ,  H01L21/8247

    CPC分类号： G11C16/06 ,  H01L21/28273 ,  H01L27/11519 ,  H01L27/11558 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7885

    摘要： Non-volatile memory (NVM) devices are disclosed. In one aspect, a NVM device may include a substrate, and a field-effect transistor (FET). The FET may include a first doped region in the substrate and a second doped region in the substrate. The first and the second doped regions may define a channel region of the substrate between them. An insulating layer may overlie the channel region. A floating gate may overlie the insulating layer. Charge of an amount that encodes a value may be stored on the floating gate. The floating gate and the first and the second doped regions may be shaped such that the floating gate defines with the first doped region a first border of a first length, and the floating gate defines with the second doped region a second border of a second length that is less than 90% of the first length.

    摘要翻译： 公开了非易失性存储器（NVM）装置。 一方面，NVM器件可以包括衬底和场效应晶体管（FET）。 FET可以包括衬底中的第一掺杂区域和衬底中的第二掺杂区域。 第一和第二掺杂区域可以在它们之间限定衬底的沟道区域。 绝缘层可以覆盖沟道区域。 浮动栅极可以覆盖绝缘层。 可以将数值编码的费用存储在浮动门上。 浮置栅极和第一和第二掺杂区域可以被成形为使得浮动栅极与第一掺杂区域限定第一长度的第一边界，并且浮置栅极与第二掺杂区域限定第二边界的第二边界 小于第一长度的90％。

    Semiconductor device incorporating thyristor-based memory and strained silicon
    29.
    发明授权
    Semiconductor device incorporating thyristor-based memory and strained silicon 失效
    包含晶闸管的存储器和应变硅的半导体器件

    公开(公告)号：US07326969B1

    公开(公告)日：2008-02-05

    申请号：US11004712

    申请日：2004-12-02

    申请人： Andrew E. Horch

    发明人： Andrew E. Horch

    IPC分类号： H01L29/423

    CPC分类号： H01L29/7436 ,  H01L27/1027 ,  H01L27/1203

    摘要： A semiconductor memory device may comprise a thyristor-based memory having some portions formed in strained silicon, and other portions formed in relaxed silicon. In a further embodiment, a thyristor in the thyristor-based memory may be formed in a region of relaxed silicon germanium, while an access device to the thyristor-based memory may have a body region incorporating a portion of a layer of strained silicon. In yet a further embodiment, different regions of the thyristor may be formed in vertical aligned relationship relative to an upper surface of the relaxed silicon germanium. For this embodiment, the thyristor may be formed substantially within the depth of the relaxed silicon germanium layer. In a method of forming the semiconductor device, relaxed silicon may be deposited over exposed regions of a silicon substrate, and a thin layer of strained silicon formed over a portion of the substrate having silicon germanium.

    摘要翻译： 半导体存储器件可以包括在应变硅中形成的一些部分的基于晶闸管的存储器，以及形成在松弛硅中的其它部分。 在另一个实施例中，基于晶闸管的存储器中的晶闸管可以形成在松散的硅锗的区域中，而到基于晶闸管的存储器的访问器件可以具有并入一层应变硅的体区。 在又一个实施例中，晶闸管的不同区域可以相对于松弛硅锗的上表面以垂直对准的关系形成。 对于该实施例，晶闸管可以基本上形成在松弛硅锗层的深度内。 在形成半导体器件的方法中，可以在硅衬底的暴露区域上沉积松弛的硅，并且在具有硅锗的衬底的一部分上形成薄层的应变硅。