公开(公告)号：US09690953B2

公开(公告)日：2017-06-27

申请号：US14212049

申请日：2014-03-14

Applicant: Apple Inc.

Inventor： Andrew W. Vogan ,  Matthew J. Byom ,  Alexander C. Sanks ,  Daniel J. Post ,  Hari Hara Kumar Maharaj ,  Nir Jacob Wakrat ,  Kenneth L. Herman

IPC: G06F21/00 ,  G06F21/79

CPC classification number: G06F21/79 ,  G06F2221/2107

Abstract: Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.

公开(公告)号：US10977119B2

公开(公告)日：2021-04-13

申请号：US16382046

申请日：2019-04-11

Applicant: Apple Inc.

Inventor： Eran Roll ,  Stas Mouler ,  Matthew J. Byom ,  Andrew W. Vogan ,  Muhammad N. Ashraf ,  Elad Harush ,  Roman Guy

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52 ,  G11C29/04 ,  G11B20/18

Abstract: Disclosed are techniques for managing parity information for data stored on a storage device. A method can be implemented at a computing device communicably coupled to the storage device, and include (1) receiving a request to write data into a data band of the storage device, (2) writing the data into stripes of the data band, comprising, for each stripe of the data band: (i) calculating first parity information for the data written into the stripe, (ii) writing the first parity information into a volatile memory, and (iii) in response to determining that a threshold number of stripes have been written: converting the first parity information into smaller second parity information, and (3) in response to determining that the data band is read-verified: (i) converting the second parity information into smaller third parity information, and (ii) storing the smaller third parity information into a parity band of the storage device.

公开(公告)号：US20200264792A1

公开(公告)日：2020-08-20

申请号：US16277230

申请日：2019-02-15

Applicant: Apple Inc.

Inventor： Alexander Paley ,  Andrew W. Vogan

IPC: G06F3/06

Abstract: Systems and methods for balancing multiple partitions of non-volatile memory devices are provided. Embodiments discussed herein execute a balance proportion scheme in connection with a NVM that is partitioned to have multiple partition types. Each partition type has an associated endurance that defines an average number of program/erase (P/E) cycles it can endure before it reaches failure. For example, a first partition type may have a substantially greater endurance than a second partition type. The balance proportion scheme ensures that, even though each partition type has a different associated endurance, all partition types are used proportionally with respect to each other to balance their respective P/E cycles. This way, both partition types will reach the upper limits of their respective endurance levels out at approximately the same time.

公开(公告)号：US10552077B2

公开(公告)日：2020-02-04

申请号：US15721285

申请日：2017-09-29

Applicant: Apple Inc.

Inventor： Andrew W. Vogan

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: Disclosed herein are techniques for managing partitions on a storage device. A method can include (1) identifying a storage capacity of the storage device, (2) generating a first data structure that defines a first partition on the storage device, where the first partition consumes a first amount of the storage capacity, and (3) generating a second data structure that defines a second partition on the storage device, where the second partition consumes at least a portion of a remaining amount of the storage capacity relative to the first amount. In response to receiving a shrink request directed to the first partition, the method can further include (4) identifying a first utilized area within the first partition that will no longer be utilized as a result of the shrink request, and (5) updating first information in the first data structure to indicate that the first utilized area is unutilized.

公开(公告)号：US10133506B2

公开(公告)日：2018-11-20

申请号：US15854299

申请日：2017-12-26

Applicant: Apple Inc.

Inventor： Andrew W. Vogan ,  Charan Srinivasan ,  Matthew J. Byom

IPC: G11C7/04 ,  G06F3/06

Abstract: Systems and methods for managing data in non-volatile memory devices across a large range of operating temperatures are provided. Embodiments discussed herein selectively reprogram previously programmed data at a temperature that better enables the data to be read regardless of where within the range of operating temperatures the data is being read. Circuitry and methods discussed herein can keep track of a program temperature associated with each portion of non-volatile memory and use this information along with other criteria to selectively perform temperature based moves of data. This enables a mechanism for data to programmed in out-of-bounds temperature ranges to be reprogrammed within an in-bounds temperatures range so that a temperature delta between the reprogrammed temperature and the read operation temperature is below a threshold that ensure efficient and error free read operations to be performed.

公开(公告)号：US20180046402A1

公开(公告)日：2018-02-15

申请号：US15232253

申请日：2016-08-09

Applicant: Apple Inc.

Inventor： Andrew W. Vogan ,  Charan Srinivasan ,  Matthew J. Byom

IPC: G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: Systems and methods for managing data in non-volatile memory devices across a large range of operating temperatures are provided. Embodiments discussed herein selectively reprogram previously programmed data at a temperature that better enables the data to be read regardless of where within the range of operating temperatures the data is being read. Circuitry and methods discussed herein can keep track of a program temperature associated with each portion of non-volatile memory and use this information along with other criteria to selectively perform temperature based moves of data. This enables a mechanism for data to programmed in out-of-bounds temperature ranges to be reprogrammed within an in-bounds temperatures range so that a temperature delta between the reprogrammed temperature and the read operation temperature is below a threshold that ensure efficient and error free read operations to be performed.

公开(公告)号：US09891859B1

公开(公告)日：2018-02-13

申请号：US15232253

申请日：2016-08-09

Applicant: Apple Inc.

Inventor： Andrew W. Vogan ,  Charan Srinivasan ,  Matthew J. Byom

IPC: G11C7/04 ,  G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: Systems and methods for managing data in non-volatile memory devices across a large range of operating temperatures are provided. Embodiments discussed herein selectively reprogram previously programmed data at a temperature that better enables the data to be read regardless of where within the range of operating temperatures the data is being read. Circuitry and methods discussed herein can keep track of a program temperature associated with each portion of non-volatile memory and use this information along with other criteria to selectively perform temperature based moves of data. This enables a mechanism for data to programmed in out-of-bounds temperature ranges to be reprogrammed within an in-bounds temperatures range so that a temperature delta between the reprogrammed temperature and the read operation temperature is below a threshold that ensure efficient and error free read operations to be performed.

公开(公告)号：US09268495B2

公开(公告)日：2016-02-23

申请号：US13965109

申请日：2013-08-12

Applicant: Apple Inc.

Inventor： Andrew W. Vogan

IPC: G06F3/00 ,  G06F3/06

CPC classification number: G06F3/0634 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0688

Abstract: In one embodiment, a memory system for managing priority based Input Output (I/O) command queuing for nonvolatile electrically erasable semiconductor memory comprises one or more banks of electrically erasable semiconductor memory coupled to a storage processor. The storage processor can processes access requests for the memory, and has components including: a command interface, an expectation table, and a mode selector. The command interface receives memory access requests, which include a tag to identify the request, and an external priority associated with the request. The expectation table includes a set of times associated with each of the external priority levels, which indicate the period in which a request having the external priority is expected. The mode selector selects from a set of storage processor operation modes including a standard mode and a preemption mode.

Abstract translation: 在一个实施例中，用于管理用于非易失性电可擦除半导体存储器的基于优先级的输入输出（I / O）命令排队的存储器系统包括耦合到存储处理器的一个或多个电可擦除半导体存储器组。 存储处理器可以处理对存储器的访问请求，并且具有包括命令接口，期望表和模式选择器的组件。 命令接口接收存储器访问请求，其中包括用于标识请求的标签以及与请求相关联的外部优先级。 期望表包括与每个外部优先级相关联的一组时间，其指示期望具有外部优先级的请求的周期。 模式选择器从包括标准模式和抢占模式的一组存储处理器操作模式中进行选择。

公开(公告)号：US20140281687A1

公开(公告)日：2014-09-18

申请号：US13829692

申请日：2013-03-14

Applicant: APPLE INC.

Inventor： Andrew W. Vogan ,  Daniel J. Post

IPC: G06F11/16

CPC classification number: G06F11/1666 ,  G06F11/073 ,  G06F11/1068 ,  G06F12/0246 ,  G11C29/808 ,  G11C29/82

Abstract: Systems and methods are disclosed for improving performance of a system having non-volatile memory (“NVM”). The system can vertically re-vector defective blocks of a user region of the NVM to other blocks having the same plane or die's plane (“DIP”) but corresponding to a dead region of the NVM. Then, the system can select any band with more than one defective block and vertically re-vector one of its defective blocks to a band that has no defective blocks. At run-time, the system can monitor the number of vertical re-vectors per DIP. If at least one vertical re-vector has been performed on all DIPs of the NVM, a band of the user region can be allocated for the dead region.

Abstract translation: 公开了用于改善具有非易失性存储器（“NVM”）的系统的性能的系统和方法。 该系统可以垂直地将NVM的用户区域的缺陷块重新向量到具有相同平面或管芯平面（“DIP”）但对应于NVM的死区的其他块。 然后，系统可以选择具有多于一个缺陷块的任何频带，并将其缺陷块中的一个垂直重新矢量到没有有缺陷块的频带。 在运行时，系统可以监控每个DIP的垂直重新向量的数量。 如果在NVM的所有DIP上执行了至少一个垂直重新向量，则可以为死区分配用户区域的频带。

公开(公告)号：US20140281588A1

公开(公告)日：2014-09-18

申请号：US14212049

申请日：2014-03-14

Applicant: Apple Inc.

Inventor： Andrew W. Vogan ,  Matthew J. Byom ,  Alexander C. Sanks ,  Daniel J. Post ,  Hari Hara Kumar Maharaj ,  Nir Jacob Wakrat ,  Kenneth L. Herman

IPC: H04L9/08

CPC classification number: G06F21/79 ,  G06F2221/2107

Abstract: Systems and methods are disclosed for generating efficient reads for a system having non-volatile memory (“NVM”). A read command can be separated by a host processor of the system into two phases: a) transmitting a command to a storage processor of the system, where the command is associated with one or more logical addresses, and b) generating data transfer information. The host processor can generate the data transfer information while the storage processor is processing the command from the host processor. Once the data transfer information has been generated and data has been read from the NVM, the data can be transferred.

Abstract translation: 公开了用于为具有非易失性存储器（“NVM”）的系统生成有效读取的系统和方法。 读取命令可以由系统的主机处理器分成两个阶段：a）将命令发送到系统的存储处理器，其中命令与一个或多个逻辑地址相关联，以及b）生成数据传输信息。 主机处理器可以在存储处理器正在处理来自主机处理器的命令时产生数据传输信息。 一旦生成了数据传输信息，并且已经从NVM读取了数据，则可以传送数据。