公开(公告)号：US20160328322A1

公开(公告)日：2016-11-10

申请号：US14705506

申请日：2015-05-06

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Harshavardhan Kaushikkar ,  Munetoshi Fukami ,  Gurjeet S. Saund ,  Manu Gulati ,  Shinye Shiu

IPC: G06F12/08 ,  G06F9/52

Abstract: An apparatus for processing memory requests from a functional unit in a computing system is disclosed. The apparatus may include an interface that may be configured to receive a request from the functional. Circuitry may be configured initiate a speculative read access command to a memory in response to a determination that the received request is a request for data from the memory. The circuitry may be further configured to determine, in parallel with the speculative read access, if the speculative read will result in an ordering or coherence violation.

Abstract translation: 公开了一种用于处理来自计算系统中的功能单元的存储器请求的装置。 该装置可以包括可被配置为从功能接收请求的接口。 响应于确定接收到的请求是来自存储器的数据的请求，可以将电路配置为向存储器发起推测性读取访问命令。 电路还可以被配置为与推测性读取访问并行地确定如果推测性读取将导致排序或一致性违规。

公开(公告)号：US20160116969A1

公开(公告)日：2016-04-28

申请号：US14980912

申请日：2015-12-28

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  Cyril de la Cropte de Chanterac ,  Manu Gulati ,  Pulkit Desai ,  Rong Zhang Hu

IPC: G06F1/32 ,  G06F12/08

CPC classification number: G06F1/3275 ,  G06F1/3218 ,  G06F1/3287 ,  G06F3/14 ,  G06F12/0873 ,  G06F2212/455 ,  G09G5/001 ,  G09G5/393 ,  G09G5/395 ,  G09G2330/02 ,  G09G2330/021 ,  G09G2360/121

Abstract: In an embodiment, a system includes a memory controller that includes a memory cache and a display controller configured to control a display. The system may be configured to detect that the images being displayed are essentially static, and may be configured to cause the display controller to request allocation in the memory cache for source frame buffer data. In some embodiments, the system may also alter power management configuration in the memory cache to prevent the memory cache from shutting down or reducing its effective size during the idle screen case, so that the frame buffer data may remain cached. During times that the display is dynamically changing, the frame buffer data may not be cached in the memory cache and the power management configuration may permit the shutting down/size reduction in the memory cache.

Abstract translation: 在一个实施例中，系统包括存储器控制器，其包括存储器高速缓存和被配置为控制显示器的显示控制器。 系统可以被配置为检测正在显示的图像基本上是静态的，并且可以被配置为使得显示控制器请求在存储器高速缓存中分配源帧缓冲器数据。 在一些实施例中，系统还可以改变存储器高速缓存中的功率管理配置，以防止存储器高速缓存在空闲屏幕情况期间关闭或减小其有效大小，使得帧缓冲器数据可以保持高速缓存。 在显示器动态改变的时间期间，帧缓冲器数据可能不被缓存在存储器高速缓存中，并且电源管理配置可以允许存储器高速缓存中的关闭/大小减小。

公开(公告)号：US09218286B2

公开(公告)日：2015-12-22

申请号：US13629196

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/084 ,  G06F2212/601 ,  G06F2212/6046

Abstract: Methods and apparatuses for processing partial write requests in a system cache within a memory controller. When a write request that updates a portion of a cache line misses in the system cache, the write request writes the data to the system cache without first reading the corresponding cache line from memory. The system cache includes error correction code bits which are redefined as word mask bits when a cache line is in a partial dirty state. When a read request hits on a partial dirty cache line, the partial data is written to memory using a word mask. Then, the corresponding full cache line is retrieved from memory and stored in the system cache.

Abstract translation: 用于在存储器控制器内的系统高速缓存中处理部分写入请求的方法和装置。 当更新高速缓存行的一部分的写请求在系统高速缓存中丢失时，写入请求将数据写入系统高速缓存，而无需从存储器读取相应的高速缓存行。 系统高速缓存包括当高速缓存线处于部分脏状态时被重新定义为字屏蔽位的纠错码位。 当读请求命中部分脏缓存行时，部分数据将使用字掩码写入存储器。 然后，从存储器检索相应的完整高速缓存行并将其存储在系统高速缓存中。

公开(公告)号：US09218040B2

公开(公告)日：2015-12-22

申请号：US13629563

申请日：2012-09-27

Applicant: Apple Inc.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  Rong Zhang Hu

IPC: G06F1/32

CPC classification number: G06F1/3225 ,  G06F2212/601

Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and individual ways are powered down when cache activity is low. A maximum active way configuration register is set by software and determines the maximum number of ways which are permitted to be active. When searching for a cache line replacement candidate, a linear feedback shift register (LFSR) is used to select from the active ways. This ensures that each active way has an equal chance of getting picked for finding a replacement candidate when one or more of the ways are inactive.

Abstract translation: 用于降低存储器控制器内的系统高速缓存的功耗的方法和装置。 系统缓存包含多种方式，缓存活动较低时，各种方式都会关闭。 最大有效方式配置寄存器由软件设置，并确定允许有效的最大路数。 当搜索高速缓存行替换候选时，线性反馈移位寄存器（LFSR）用于从活动方式中选择。 这确保了当一个或多个方式处于非活动状态时，每个活动方式都有相同的机会被选中以找到替换候选。

公开(公告)号：US08984227B2

公开(公告)日：2015-03-17

申请号：US13855174

申请日：2013-04-02

Applicant: Apple Inc.

Inventor： Shinye Shiu ,  Sukalpa Biswas ,  Wolfgang H. Klingauf ,  Rong Zhang Hu

IPC: G06F12/02 ,  G06F1/32 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F1/3275 ,  G06F12/0864 ,  G06F12/123 ,  G06F12/126 ,  G06F2212/1028 ,  G06F2212/601 ,  Y02D10/13

Abstract: Methods and apparatuses for reducing power consumption of a system cache within a memory controller. The system cache includes multiple ways, and each way is powered independently of the other ways. A target active way count is maintained and the system cache attempts to keep the number of currently active ways equal to the target active way count. The bandwidth and allocation intention of the system cache is monitored. Based on these characteristics, the system cache adjusts the target active way count up or down, which then causes the number of currently active ways to rise or fall in response to the adjustment to the target active way count.

Abstract translation: 用于降低存储器控制器内的系统高速缓存的功耗的方法和装置。 系统缓存包含多种方式，每种方式独立于其他方式供电。 维护目标活动方式计数，并且系统缓存尝试将当前活动方式的数量保持等于目标活动方式计数。 监控系统缓存的带宽和分配意图。 基于这些特征，系统高速缓存调整目标活动方式向上或向下计数，从而响应于对目标活动方式计数的调整，使当前活动方式的数量上升或下降。

公开(公告)号：US20140095800A1

公开(公告)日：2014-04-03

申请号：US13629865

申请日：2012-09-28

Applicant: APPLE INC.

Inventor： Sukalpa Biswas ,  Shinye Shiu ,  James Wang ,  Robert Hu

IPC: G06F12/08

CPC classification number: G06F12/126 ,  G06F1/3225 ,  G06F12/0842

Abstract: Methods and apparatuses for releasing the sticky state of cache lines for one or more group IDs. A sticky removal engine walks through the tag memory of a system cache looking for matches with a first group ID which is clearing its cache lines from the system cache. The engine clears the sticky state of each cache line belonging to the first group ID. If the engine receives a release request for a second group ID, the engine records the current index to log its progress through the tag memory. Then, the engine continues its walk through the tag memory looking for matches with either the first or second group ID. The engine wraps around to the start of the tag memory and continues its walk until reaching the recorded index for the second group ID.

Abstract translation: 用于释放用于一个或多个组ID的高速缓存行的粘性状态的方法和装置。 粘性移除引擎遍历系统缓存的标签存储器，寻找与从系统高速缓存清除其高速缓存行的第一组ID的匹配。 引擎清除属于第一组ID的每个高速缓存行的粘性状态。 如果引擎接收到第二组ID的释放请求，则引擎记录当前索引以通过标记存储器记录其进度。 然后，引擎继续通过标签存储器查找与第一或第二组ID的匹配。 发动机卷绕到标签存储器的开头，并继续其行进直到达到第二组ID的记录索引。

公开(公告)号：US20140095777A1

公开(公告)日：2014-04-03

申请号：US13629894

申请日：2012-09-28

Applicant: APPLE INC.

Inventor： Sukalpa Biswas ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F1/3287 ,  G06F1/3275 ,  G06F12/0802 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/171

Abstract: Methods and apparatuses for reducing leakage power in a system cache within a memory controller. The system cache is divided into multiple small sections, and each section is supplied with power from a separately controllable power supply. When a section is not being accessed, the voltage supplied to the section is reduced to a voltage sufficient for retention of data but not for access. Incoming requests are grouped together based on which section of the system cache they target. When enough requests that target a given section have accumulated, the voltage supplied to the given section is increased to a voltage sufficient for access. Then, once the given section has enough time to ramp-up and stabilize at the higher voltage, the waiting requests may access the given section in a burst of operations.

Abstract translation: 用于减少存储器控制器内的系统高速缓存中的泄漏功率的方法和装置。 系统缓存分为多个小部分，每个部分都由独立可控的电源供电。 当一个部分没有被访问时，提供给该部分的电压降低到足以保留数据但不能访问的电压。 根据目标系统缓存的哪个部分将传入请求分组在一起。 当针对给定部分的足够的请求已经累积时，提供给给定部分的电压增加到足以进行访问的电压。 然后，一旦给定的部分有足够的时间来提升和稳定在较高的电压，则等待的请求可以在一连串的操作中访问给定的部分。

公开(公告)号：US20140089602A1

公开(公告)日：2014-03-27

申请号：US13629196

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Sukalpa Biswas ,  Shinye Shiu

IPC: G06F12/08

CPC classification number: G06F12/0804 ,  G06F12/084 ,  G06F2212/601 ,  G06F2212/6046

Abstract: Methods and apparatuses for processing partial write requests in a system cache within a memory controller. When a write request that updates a portion of a cache line misses in the system cache, the write request writes the data to the system cache without first reading the corresponding cache line from memory. The system cache includes error correction code bits which are redefined as word mask bits when a cache line is in a partial dirty state. When a read request hits on a partial dirty cache line, the partial data is written to memory using a word mask. Then, the corresponding full cache line is retrieved from memory and stored in the system cache.

Abstract translation: 用于在存储器控制器内的系统高速缓存中处理部分写入请求的方法和装置。 当更新高速缓存行的一部分的写请求在系统高速缓存中丢失时，写入请求将数据写入系统高速缓存，而无需从存储器读取相应的高速缓存行。 系统高速缓存包括当高速缓存线处于部分脏状态时被重新定义为字屏蔽位的纠错码位。 当读请求命中部分脏缓存行时，部分数据将使用字掩码写入存储器。 然后，从存储器检索相应的完整高速缓存行并将其存储在系统高速缓存中。

公开(公告)号：US20140089592A1

公开(公告)日：2014-03-27

申请号：US13629172

申请日：2012-09-27

Applicant: APPLE INC.

Inventor： Sukalpa Biswas ,  Shinye Shiu

IPC: G06F12/12

CPC classification number: G06F12/0862 ,  G06F1/3225 ,  G06F1/3275 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods and apparatuses for processing speculative read requests in a system cache within a memory controller. To expedite a speculative read request, the request is sent on parallel paths through the system cache. A first path goes through a speculative read engine to determine if the speculative read request meets the conditions for accessing memory. A second path involves performing a tag lookup to determine if the data referenced by the request is already in the system cache. If the speculative read request meets the conditions for accessing memory, the request is sent to a miss queue where it is held until a confirm or cancel signal is received from the tag lookup mechanism.

Abstract translation: 用于在存储器控制器内的系统高速缓存中处理推测读请求的方法和装置。 为了加快推测读请求，请求通过系统缓存的并行路径发送。 第一条路径经过推测读取引擎，以确定推测性读取请求是否满足访问内存的条件。 第二条路径涉及执行标签查找以确定请求引用的数据是否已经在系统高速缓存中。 如果推测性读取请求满足访问存储器的条件，则该请求被发送到丢失队列，在该队列中保持该请求，直到从标签查找机制接收到确认或取消信号。