公开(公告)号：US20190253084A1

公开(公告)日：2019-08-15

申请号：US15896015

申请日：2018-02-13

Applicant: Arm Limited

Inventor： Vivek Asthana ,  Jitendra Dasani ,  Amit Chhabra

IPC: H03M13/00 ,  G11C16/08 ,  G11C8/10 ,  G11C8/08

CPC classification number: H03M13/611 ,  G11C8/08 ,  G11C8/10 ,  G11C11/41 ,  G11C16/08

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include first decoding circuitry that receives an address and partially decodes the address to generate a partially decoded address. The integrated circuit may include second decoding circuitry that receives the partially decoded address, generates a decoded address, and provides the decoded address to a wordline. The integrated circuit may include encoding circuitry that receives the decoded address from the wordline and encodes the decoded address to generate an encoded address. The integrated circuit may include comparing circuitry that receives the encoded address and compares the encoded address with the address to detect faults in the memory circuitry.

公开(公告)号：US20190244656A1

公开(公告)日：2019-08-08

申请号：US15891212

申请日：2018-02-07

Applicant: Arm Limited

Inventor： Yicong Li ,  Andy Wangkun Chen ,  Sharryl Renee Dettmer ,  Lalit Gupta ,  Jitendra Dasani ,  Yeon Jun Park ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/4097 ,  G11C7/18 ,  G11C11/419 ,  H01L27/11

Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry. The memory circuitry may include a first array of bitcells accessible with a first bitline pair and a second array of bitcells accessible with a second bitline pair. The integrated circuit may include first transition coupling circuitry for accessing jumper bitline pairs and coupling the jumper bitline pairs to column multiplexer circuitry. The integrated circuit may include second transition coupling circuitry for accessing the first array of bitcells or the second array of bitcells and providing a data output signal to the jumper bitline pairs. The first bitline pair and the second bitline pair may be on a lower metal layer, and the jumper bitline pairs may be on a higher metal layer.

公开(公告)号：US20190066770A1

公开(公告)日：2019-02-28

申请号：US15684255

申请日：2017-08-23

Applicant: ARM Limited

Inventor： Rajiv Kumar Sisodia ,  Navin Agarwal ,  Shri Sagar Dwivedi ,  Jitendra Dasani ,  Fakhruddin Ali Bohra ,  Lalit Gupta ,  Daksheshkumar Maganbhai Malaviya

IPC: G11C11/419

Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include read circuitry coupled to bitlines, and the read circuitry may be activated based on a read select signal to perform a read operation on the bitlines. The integrated circuit may include write circuitry coupled to the bitlines, and the write circuitry may be activated based on a write select signal to perform a write operation on the bitlines. The integrated circuit may include bitline discharge control circuitry coupled to the bitlines and the write circuitry, and the bitline discharge control circuitry may control the bitline discharge of the bitlines during the read operation so as to restrict a false read on the bitlines by providing a discharge boundary for the bitlines during the read operation.

公开(公告)号：US10147482B2

公开(公告)日：2018-12-04

申请号：US15462549

申请日：2017-03-17

Applicant: ARM Limited

Inventor： Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/418

Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

公开(公告)号：US20180268894A1

公开(公告)日：2018-09-20

申请号：US15462549

申请日：2017-03-17

Applicant: ARM Limited

Inventor： Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C7/227 ,  G11C11/418

Abstract: A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

公开(公告)号：US09953701B1

公开(公告)日：2018-04-24

申请号：US15439899

申请日：2017-02-22

Applicant: ARM Limited

Inventor： Fakhruddin Ali Bohra ,  Lalit Gupta ,  Shri Sagar Dwivedi ,  Jitendra Dasani

IPC: G11C11/34 ,  G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: An SRAM with a first bitcell array having a first density and a first access speed, and a second bitcell array having a second density larger than the first density and a second access speed less than the first access speed. The SRAM further includes a first set of wordline drivers coupled to the first bitcell array, a second set of wordline drivers coupled to the second bitcell array, and a row decoder coupled to both the first and second bitcell arrays.