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    Coupling compensation circuitry
    23.
    发明授权
    Coupling compensation circuitry 有权

    公开(公告)号：US10755774B2

    公开(公告)日：2020-08-25

    申请号：US16820487

    申请日：2020-03-16

    Applicant: Arm Limited

    Inventor： Vivek Nautiyal ,  Lalit Gupta ,  Fakhruddin Ali Bohra ,  Shri Sagar Dwivedi

    IPC: G11C11/00 ,  G11C11/419 ,  G11C11/412

    Abstract: Various implementations described herein refer to an integrated circuit having a bitcell coupled to a bitline and a column multiplexer device coupled to the bitline between the bitcell and an output of a write driver. The integrated circuit may include a first signal line coupled to a gate of the column multiplexor device that provides a first transition signal. The integrated circuit may include a second signal line coupled to an input of the write driver that provides a second transitioning signal, and the second transition signal transitions substantially similar to the first transitioning signal. The integrated circuit may include a coupling device coupled between the first signal line and the second signal line.

    High-Speed Memory Architecture
    24.
    发明申请
    High-Speed Memory Architecture 审中-公开

    公开(公告)号：US20200005836A1

    公开(公告)日：2020-01-02

    申请号：US16024449

    申请日：2018-06-29

    Applicant: Arm Limited

    Inventor： Lalit Gupta ,  Fakhruddin Ali Bohra ,  Jitendra Dasani ,  Shri Sagar Dwivedi ,  Vivek Nautiyal ,  Gaurav Rattan Singla

    IPC: G11C7/12 ,  G11C7/18 ,  G11C7/22 ,  G11C8/14

    Abstract: Various implementations described herein refer to an integrated circuit having memory circuitry having multiple banks of bitcell arrays including a first pair of bank arrays and a second pair of bank arrays. The first pair of bank arrays may have a first number of rows, and the second pair of bank arrays have a second number of rows that is different than the first number of rows. The integrated circuit may include bank multiplexer circuitry that is coupled to the first pair of bank arrays via a first channel and the second pair of bank arrays via a second channel that is separate from the first channel. The bank multiplexer circuitry may provide an output data signal from the first pair of bank arrays or the second pair of bank arrays based on a control signal.

    Integrated Circuit Using Discharging Circuitries for Bit Lines
    25.
    发明申请
    Integrated Circuit Using Discharging Circuitries for Bit Lines 审中-公开

    公开(公告)号：US20190325949A1

    公开(公告)日：2019-10-24

    申请号：US15960482

    申请日：2018-04-23

    Applicant: Arm Limited

    Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Shri Sagar Dwivedi ,  Fakhruddin Ali Bohra

    IPC: G11C11/419 ,  G11C11/412

    Abstract: Various implementations described herein may refer to an integrated circuit using discharging circuitries for bit lines. In one implementation, an integrated circuit may include a memory array having memory cells, where the memory cells are arranged into columns and configured to be accessed using bit line pairs. The integrated circuit may also include discharging circuitries to selectively discharge the bit line pairs, where a respective discharging circuitry is coupled to a negative supply voltage node of a respective column of memory cells. The respective discharging circuitry may discharge a bit line pair of the respective column to a first voltage when the bit line pair is selected for a memory operation, and may discharge the bit line pair of the respective column to a second voltage when the bit line pair is not selected for a memory operation, where the second voltage is greater than the first voltage.

    Dummy wordline tracking circuitry
    27.
    发明授权
    Dummy wordline tracking circuitry 有权

    公开(公告)号：US10269416B1

    公开(公告)日：2019-04-23

    申请号：US15789715

    申请日：2017-10-20

    Applicant: ARM Limited

    Inventor： Lalit Gupta ,  Jitendra Dasani ,  Vivek Nautiyal ,  Fakhruddin Ali Bohra

    IPC: G11C11/417 ,  G11C11/418 ,  H01L23/528 ,  H01L27/11 ,  G11C11/412

    Abstract: Various implementations described herein are directed to an integrated circuit. The integrated circuit may include dummy wordline circuitry having a dummy wordline driver coupled to multiple dummy wordline loads via a dummy wordline. The integrated circuit may include demultiplexer circuitry coupled to a first path of the dummy wordline between the dummy wordline driver and the multiple dummy wordline loads. The integrated circuit may include multiplexer circuitry coupled to a second path of the dummy wordline between the multiple dummy wordline loads and a dummy bitline load. The demultiplexer circuitry and the multiplexer circuitry may be controlled with one or more selection signals to select at least one of the multiple dummy wordline loads.

    Bitline write assist circuitry
    28.
    发明授权
    Bitline write assist circuitry 有权

    公开(公告)号：US10217496B1

    公开(公告)日：2019-02-26

    申请号：US15907951

    申请日：2018-02-28

    Applicant: Arm Limited

    Inventor： Vivek Nautiyal ,  Jitendra Dasani ,  Satinderjit Singh ,  Shri Sagar Dwivedi ,  Bo Zheng ,  Fakhruddin Ali Bohra

    IPC: G11C7/00 ,  G11C7/12 ,  G11C7/10 ,  G11C11/4097 ,  G11C11/419

    Abstract: Various implementations described herein are directed to an integrated circuit with memory circuitry having an array of bitcells that are accessible via multiple bitlines. The integrated circuit may include a write driver coupled to at least one bitline of the multiple bitlines through a column multiplexer. The integrated circuit may include a pass transistor coupled to the write driver and the column multiplexer via a write data line. The integrated circuit may include a charge storage device coupled between the pass transistor and write assist enable circuitry. The integrated circuit may include a transmission gate coupled to a gate of the write driver. The integrated circuit may include a clamp transistor coupled between the gate of write driver and the charge storage device such that the clamp transistor receives a voltage assist signal from the charge storage device at the gate of the write driver.

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