公开(公告)号：US08179711B2

公开(公告)日：2012-05-15

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

公开(公告)号：US07515459B2

公开(公告)日：2009-04-07

申请号：US11315129

申请日：2005-12-23

申请人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

发明人： Sang-beom Kang ,  Du-eung Kim ,  Beak-hyung Cho ,  Hye-jin Kim

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/79

摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.

摘要翻译： 提供了一种编程包括多个存储单元的存储器阵列的方法。 存储器单元可以包括相变存储元件。 在一个方面，该方法包括将第一至第n电流脉冲连续地应用于要被编程到第一状态（例如，结晶状态）的每个存储器单元，其中第一至第n电流脉冲的电流幅度随着每个 连续脉冲，并且其中第一至第n电流脉冲的脉冲持续时间随着每个连续脉冲而增加。

公开(公告)号：US07876609B2

公开(公告)日：2011-01-25

申请号：US12720918

申请日：2010-03-10

申请人： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

发明人： Kwang-jin Lee ,  Choong-keun Kwak ,  Du-eung Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C13/0064

摘要： In a nonvolatile memory device, a program operation is performed on a plurality of nonvolatile memory cells by programming data having a first logic state in a first group among a plurality of selected memory cells selected from the plurality of nonvolatile memory cells during a first program interval of the program operation, and thereafter, programming data having a second logic state different from the first logic state in a second group among the selected memory cells during a second program interval of the program operation after the first program interval.

摘要翻译： 在非易失性存储器件中，通过在第一程序间隔期间从多个非易失性存储单元中选出的多个选择的存储单元中的第一组中编程具有第一逻辑状态的数据，对多个非易失性存储单元执行编程操作 并且此后，在所述第一编程间隔之后的所述程序操作的第二编程间隔期间，在所选择的存储单元之间具有与所述第二组中的第一逻辑状态不同的第二逻辑状态的编程数据。

公开(公告)号：US07457151B2

公开(公告)日：2008-11-25

申请号：US11319601

申请日：2005-12-29

申请人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

发明人： Woo-yeong Cho ,  Du-eung Kim ,  Sang-beom Kang ,  Choong-keun Kwak

IPC分类号： G11C11/00

CPC分类号： G11C13/0038 ,  G11C5/145 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/009

摘要： A phase change memory device of one aspect includes a memory array including a plurality of phase change memory cells, a write boosting circuit, and a write driver. The write boosting circuit boosts a first voltage and outputs a first control voltage in response to a control signal in a first operation mode, and boosts the first voltage and outputs a second control voltage in response to the control signal in a second operation mode and a third operation mode. The write driver is driven by the first control voltage in the first operation mode and writes data to a selected memory cell of the memory array.

摘要翻译： 一个方面的相变存储器件包括包括多个相变存储单元，写升压电路和写驱动器的存储器阵列。 写升压电路响应于第一操作模式中的控制信号而升高第一电压并输出第一控制电压，并且在第二操作模式中响应于控制信号升高第一电压并输出第二控制电压，并且 第三操作模式。 写入驱动器由第一操作模式中的第一控制电压驱动，并将数据写入存储器阵列的所选存储单元。

公开(公告)号：US07453716B2

公开(公告)日：2008-11-18

申请号：US11238381

申请日：2005-09-29

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00

CPC分类号： H01L27/2436 ,  G11C13/0004 ,  G11C13/003 ,  G11C2213/74 ,  G11C2213/79

摘要： In a semiconductor memory device and method, phase-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices formed of a phase-change material. Each phase-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of phase-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the phase-change memory cells of each of the phase-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a phase-change material. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the phase-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了相变存储单元，每个都包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个相变存储单元组。 每个相变存储单元组的每个相变存储单元包括形成在不同层上的多个控制晶体管和由相变材料形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个相变存储单元的电流量。

公开(公告)号：US20060256612A1

公开(公告)日：2006-11-16

申请号：US11303910

申请日：2005-12-19

申请人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

摘要： A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

摘要翻译： 提供了一种用于驱动相变存储器件的字线的方法和装置。 该方法可以包括在正常操作模式期间将未选择字线的第一电压电平和第二电压电平施加到所选择的字线，以及在备用操作模式期间将字线置于浮置状态。 相变存储装置可以包括用于驱动对应字线的多个字线驱动电路，其中多个字线驱动电路中的每一个包括驱动单元，该驱动单元将相应的字线设置为第一电压电平或第二电压电平 响应于第一控制信号，以及模式选择器，其根据相变存储器件的操作模式选择性地将第一电压电平施加到驱动单元。

公开(公告)号：US07417887B2

公开(公告)日：2008-08-26

申请号：US11303910

申请日：2005-12-19

申请人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

发明人： Beak-hyung Cho ,  Jong-soo Seo ,  Du-eung Kim ,  Woo-yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C2213/72

摘要： A method and device for driving the word lines of a phase change memory device is provided. The method may include applying a first voltage level to non-selected word lines and a second voltage level to selected word lines during a normal operational mode, and placing the word lines in a floating state during a standby operational mode. The phase change memory device may include a plurality of word line drive circuits for driving corresponding word lines, where each of the plurality of word line drive circuits includes a drive unit which sets a corresponding word line to a first voltage level or a second voltage level in response to a first control signal, and a mode selector which selectively applies the first voltage level to the driving unit according to an operational mode of the phase change memory device.

摘要翻译： 提供了一种用于驱动相变存储器件的字线的方法和装置。 该方法可以包括在正常操作模式期间将未选择字线的第一电压电平和第二电压电平施加到所选择的字线，以及在备用操作模式期间将字线置于浮置状态。 相变存储装置可以包括用于驱动对应字线的多个字线驱动电路，其中多个字线驱动电路中的每一个包括驱动单元，该驱动单元将相应的字线设置为第一电压电平或第二电压电平 响应于第一控制信号，以及模式选择器，其根据相变存储器件的操作模式选择性地将第一电压电平施加到驱动单元。

公开(公告)号：US20060209616A1

公开(公告)日：2006-09-21

申请号：US11319604

申请日：2005-12-29

申请人： Hye-jin Kim ,  Du-eung Kim ,  Beak-hyung Cho ,  Hyung-rok Oh

发明人： Hye-jin Kim ,  Du-eung Kim ,  Beak-hyung Cho ,  Hyung-rok Oh

IPC分类号： G11C8/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028

摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.

公开(公告)号：US20090168493A1

公开(公告)日：2009-07-02

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00 ,  H01L21/00 ,  H01L47/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

公开(公告)号：US07548446B2

公开(公告)日：2009-06-16

申请号：US11319604

申请日：2005-12-29

申请人： Hye-jin Kim ,  Du-eung Kim ,  Beak-hyung Cho ,  Hyung-rok Oh

发明人： Hye-jin Kim ,  Du-eung Kim ,  Beak-hyung Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028

摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.

摘要翻译： 半导体存储器件包括多个字线驱动电路，其适于响应于全局字线和地址信号的逻辑状态来控制子字线的电压电平。 字线驱动电路包括第一和第二晶体管，其被配置为当全局字线和地址信号具有第一逻辑状态并且当全局字线或地址信号具有第一电压电平时，将子字线保持在第一电压电平 第二逻辑状态。