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    Phase change memory device and associated wordline driving circuit
    2.
    发明授权
    Phase change memory device and associated wordline driving circuit 失效
    相变存储器件和相关的字线驱动电路

    公开(公告)号：US07548446B2

    公开(公告)日：2009-06-16

    申请号：US11319604

    申请日：2005-12-29

    申请人： Hye-jin Kim ,  Du-eung Kim ,  Beak-hyung Cho ,  Hyung-rok Oh

    发明人： Hye-jin Kim ,  Du-eung Kim ,  Beak-hyung Cho ,  Hyung-rok Oh

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028

    摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.

    摘要翻译： 半导体存储器件包括多个字线驱动电路，其适于响应于全局字线和地址信号的逻辑状态来控制子字线的电压电平。 字线驱动电路包括第一和第二晶体管，其被配置为当全局字线和地址信号具有第一逻辑状态并且当全局字线或地址信号具有第一电压电平时，将子字线保持在第一电压电平 第二逻辑状态。

    Nonvolatile memory devices having enhanced bit line and/or word line driving capability
    3.
    发明授权
    Nonvolatile memory devices having enhanced bit line and/or word line driving capability 有权
    具有增强的位线和/或字线驱动能力的非易失性存储器件

    公开(公告)号：US07397681B2

    公开(公告)日：2008-07-08

    申请号：US11348432

    申请日：2006-02-06

    申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

    发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

    IPC分类号： G11C27/00

    CPC分类号： G11C11/5678 ,  G11C13/0004

    摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

    摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

    Nonvolatile memory devices having enhanced bit line and/or word line driving capability
    4.
    发明申请
    Nonvolatile memory devices having enhanced bit line and/or word line driving capability 有权
    具有增强的位线和/或字线驱动能力的非易失性存储器件

    公开(公告)号：US20060215440A1

    公开(公告)日：2006-09-28

    申请号：US11348432

    申请日：2006-02-06

    申请人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

    发明人： Beak-hyung Cho ,  Du-eung Kim ,  Choong-keun Kwak ,  Hyung-rok Oh ,  Woo-yeong Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C11/5678 ,  G11C13/0004

    摘要： Phase-changeable random access memory (PRAM) devices include a plurality of rows and columns of PRAM memory cells therein and at least one local bit line electrically coupled to a column of the PRAM memory cells. First and second bit line selection circuits are provided to increase the rate at which the at least one local bit line can be accessed and driven with a bit line signal. These first and second bit line selection circuits are configured to electrically connect first and second ends of the at least one local bit line to a global bit line during an operation to read data from a selected one of the PRAM memory cells in the column.

    摘要翻译： 相位可变随机存取存储器（PRAM）装置包括其中的多个行和列的PRAM存储器单元，以及电耦合到PRAM存储器单元的列的至少一个局部位线。 提供第一和第二位线选择电路以增加利用位线信号来访问和驱动至少一个局部位线的速率。 这些第一位线选择电路和第二位线选择电路被配置为在操作期间将至少一个局部位线的第一和第二端电连接到全局位线，以从列中的所选PRAM存储器单元读取数据。

    Phase change random access memory
    5.
    发明申请
    Phase change random access memory 有权

    公开(公告)号：US20090225590A1

    公开(公告)日：2009-09-10

    申请号：US12453420

    申请日：2009-05-11

    申请人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

    发明人： Hyung-rok Oh ,  Woo-Yeong Cho ,  Beak-hyung Cho

    IPC分类号： G11C11/00 ,  G11C7/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

    摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

    Writing driver circuit of phase-change memory
    6.
    发明授权
    Writing driver circuit of phase-change memory 有权

    公开(公告)号：US07012834B2

    公开(公告)日：2006-03-14

    申请号：US10829807

    申请日：2004-04-22

    申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    IPC分类号： G11C7/00

    CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

    摘要： A writing driver circuit of a phase-change memory array which has a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

    Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory
    7.
    发明授权
    Memory system, memory device and apparatus including writing driver circuit for a variable resistive memory 有权
    存储器系统，存储器件和装置，包括用于可变电阻存储器的写入驱动电路

    公开(公告)号：US07688621B2

    公开(公告)日：2010-03-30

    申请号：US11949299

    申请日：2007-12-03

    申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

    IPC分类号： G11C11/00

    CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

    摘要： An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

    摘要翻译： 一种装置，非易失性存储装置和非易失性存储器系统包括易失性可变电阻存储器（VRM）单元阵列和具有脉冲选择电路，电流控制电路和电流驱动电路的写入驱动器电路。 电流控制电路接收偏置电压，当数据处于第一电平时，在复位脉冲的使能持续时间期间以第二电平输出控制信号，并且在该组的使能持续时间期间输出处于第一电平的控制信号 数据处于第二级时的脉冲。 当前驱动电路在复位脉冲或设定脉冲的使能期间内向相变存储器阵列输出写入电流。 写入驱动器电路可以根据数据的逻辑电平选择复位脉冲或设置脉冲，并根据复位脉冲或设定脉冲控制施加到相变存储器阵列的电流电平。

    Phase change random access memory
    8.
    发明授权
    Phase change random access memory 有权
    相变随机存取存储器

    公开(公告)号：US07548451B2

    公开(公告)日：2009-06-16

    申请号：US11896721

    申请日：2007-09-05

    申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

    发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

    摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

    摘要翻译： 提供了一种相变随机存取（PRAM）存储器。 PRAM可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，所述补偿单元被配置为向感测节点提供补偿电流以补偿减小 由流过多个相变存储器单元之一的电流引起的感测节点的电平，以及被配置为将感测节点的电平与参考电平进行比较并输出比较结果的感测放大器。

    Phase change random access memory
    9.
    发明申请
    Phase change random access memory 有权
    相变随机存取存储器

    公开(公告)号：US20080055972A1

    公开(公告)日：2008-03-06

    申请号：US11896721

    申请日：2007-09-05

    申请人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

    发明人： Hyung-rok Oh ,  Woo-yeong Cho ,  Beak-hyung Cho

    IPC分类号： G11C11/00

    CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/004 ,  G11C2013/0054

    摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

    摘要翻译： 提供了一种相变随机存取（PRAM）存储器。 PRAM可以包括具有多个相变存储器单元的存储单元阵列和包括补偿单元和读出放大器的数据读取电路，所述补偿单元被配置为向感测节点提供补偿电流以补偿减小 由流过多个相变存储器单元之一的电流引起的感测节点的电平，以及被配置为将感测节点的电平与参考电平进行比较并输出比较结果的感测放大器。

    Semiconductor memory device
    10.
    发明授权
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：US07262990B2

    公开(公告)日：2007-08-28

    申请号：US11253626

    申请日：2005-10-20

    申请人： Beak-hyung Cho ,  Sang-beom Kang ,  Hyung-rok Oh

    发明人： Beak-hyung Cho ,  Sang-beom Kang ,  Hyung-rok Oh

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C13/0038 ,  G11C13/0069

    摘要： A semiconductor memory device includes: phase-change memory cells whose states change to a set resistance state or a reset resistance state in response to an applied current pulse; a set pulse driving circuit outputting a set current pulse having first through n-th stages in response to a first control signal and a set control signal, wherein current amounts of the first through n-th stages are sequentially reduced and are all greater than a reference current amount; a reset pulse driving circuit outputting a reset current pulse in response to a second control signal; a pull-down device activating the set pulse driving circuit and the reset pulse driving circuit in response to a third control signal; and a write driver control circuit outputting the first through third control signals in response to write data, a set pulse width control signal, and a reset pulse width control signal.

    摘要翻译： 半导体存储器件包括：响应于所施加的电流脉冲，其状态改变为设定电阻状态或复位电阻状态的相变存储器单元; 设置脉冲驱动电路，响应于第一控制信号和设定控制信号，输出具有第一至第n级的设定电流脉冲，其中第一至第n级的电流量依次减小并且均大于 参考电流量; 复位脉冲驱动电路，响应于第二控制信号输出复位电流脉冲; 响应于第三控制信号激活所述设定脉冲驱动电路和所述复位脉冲驱动电路的下拉装置; 以及响应写入数据，设定的脉冲宽度控制信号和复位脉冲宽度控制信号而输出第一至第三控制信号的写入驱动器控制电路。