公开(公告)号：US07064601B2

公开(公告)日：2006-06-20

申请号：US09955458

申请日：2001-09-18

申请人： Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G05F1/46

CPC分类号： G05F3/262

摘要： A reference voltage generating circuit includes a current mirror circuit having first and second current paths formed between a first power source terminal and a second power source terminal in which the current mirror circuit is operated in response to a voltage level of the second current path, a reference voltage output node for providing a reference voltage and being located on the second current path, an active resistance device formed on the first current path to be operated in a linear region of a current-voltage characteristic curve of the active resistance device, and a voltage supply circuit for supplying the active resistance device with an enable voltage to control the active resistance device to be operated in the linear region.

公开(公告)号：US07463511B2

公开(公告)日：2008-12-09

申请号：US11723361

申请日：2007-03-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device includes a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array includes a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit includes a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.

摘要翻译： 相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。 存储单元阵列包括多个块单元，每个块单元连接在相应的一对字线驱动器之间。 写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。 列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流 的内存块。

公开(公告)号：US20070242503A1

公开(公告)日：2007-10-18

申请号：US11723361

申请日：2007-03-19

申请人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Byung-Gil Choi ,  Choong-Keun Kwak ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/72

摘要： A phase change memory device comprises a memory cell array and a write driver circuit, and a column selection circuit. The memory cell array comprises a plurality of block units each connected between a corresponding pair of word line drivers. The write driver circuit comprises a plurality of write driver units each comprising a plurality of write drivers adapted to provide respective programming currents to a corresponding block unit among the plurality of block units. The column selection circuit is connected between the memory cell array and the write driver circuit and is adapted to select at least one of the plurality of memory blocks in response to a column selection signal to provide corresponding programming currents to the at least one of the plurality of memory blocks.

摘要翻译： 相变存储器件包括存储单元阵列和写入驱动器电路以及列选择电路。 存储单元阵列包括多个块单元，每个块单元连接在对应的一对字线驱动器之间。 写驱动器电路包括多个写驱动器单元，每个写驱动器单元包括多个写驱动器，其适于向多个块单元中的相应块单元提供相应的编程电流。 列选择电路连接在存储单元阵列和写驱动器电路之间，并且适于响应于列选择信号选择多个存储器块中的至少一个，以向多个存储单元阵列中的至少一个提供对应的编程电流 的内存块。

公开(公告)号：US6026039A

公开(公告)日：2000-02-15

申请号：US215576

申请日：1998-12-17

申请人： Du-Eung Kim ,  Choong-Keun Kwak ,  Yun-Seung Shin

发明人： Du-Eung Kim ,  Choong-Keun Kwak ,  Yun-Seung Shin

IPC分类号： H01L21/822 ,  G01R31/26 ,  G01R31/28 ,  G11C29/02 ,  G11C29/50 ,  H01L27/04 ,  G11C7/00

CPC分类号： G11C29/022 ,  G11C29/02 ,  G11C29/50 ,  G11C2029/2602 ,  G11C2029/5006

摘要： A parallel test circuit for a semiconductor memory device includes multiple data input pads, multiple data input buffers respectively connected to the data input pads for receiving write data in response to a chip selection signal during normal operation, and a switching circuit for electrically connecting the data input pads to each other in response to a current leakage test signal applied to the circuit. The circuit enables the detection of leakage current in the input data buffers at the same time that a parallel data writing test is performed, thereby reducing the total time required to test the device.

摘要翻译： 一种用于半导体存储器件的并行测试电路包括多个数据输入焊盘，分别连接到数据输入焊盘的多个数据输入缓冲器，用于在正常操作期间响应芯片选择信号接收写入数据;以及切换电路，用于电连接数据 响应于施加到电路的电流泄漏测试信号，输入焊盘彼此相连。 该电路能够在执行并行数据写入测试的同时检测输入数据缓冲器中的漏电流，从而减少测试器件所需的总时间。

公开(公告)号：US5959907A

公开(公告)日：1999-09-28

申请号：US28150

申请日：1998-02-23

申请人： Du-Eung Kim ,  Choong-Keun Kwak

发明人： Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C29/04 ,  G11C7/00 ,  G11C8/00 ,  G11C29/00

CPC分类号： G11C11/418 ,  G11C29/785 ,  G11C29/83

摘要： A redundancy circuit for a semiconductor device comprises a circuit having variable impedance changed in accordance with a chip selecting signal. The variable impedance circuit has a low impedance when the chip selecting signal is at a low level and a high impedance when the chip selecting signal is at a high level. Therefore, when the device is in a standby state, no static current flows, and when the chip is in an active state current of less than several micro amperes flows. Thus, the power dissipation of the redundancy circuit can be reduced.

摘要翻译： 用于半导体器件的冗余电路包括根据芯片选择信号而改变可变阻抗的电路。 当芯片选择信号处于低电平时，可变阻抗电路具有低阻抗，并且当芯片选择信号处于高电平时具有高阻抗。 因此，当器件处于待机状态时，不会流动静电流，并且当芯片处于活动状态时，电流小于几微安流动。 因此，可以减少冗余电路的功率消耗。

公开(公告)号：US20050007843A1

公开(公告)日：2005-01-13

申请号：US10889194

申请日：2004-07-12

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/812 ,  G11C29/806

摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.

摘要翻译： 一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址 在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

公开(公告)号：US06456547B1

公开(公告)日：2002-09-24

申请号：US09689098

申请日：2000-10-12

申请人： Hyun-Sun Mo ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Hyun-Sun Mo ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C700

CPC分类号： G11C29/83 ,  G11C7/12

摘要： A semiconductor memory device having memory cells connected with pairs of bit lines and word lines comprises a pre-charging part for pre-charging a pair of bit lines in response to a first state control signal at a stand-by mode of the semiconductor memory device; a bit line charging control part for generating a second state control signal to the pre-charging part when a stand-by current failure occurs due to defect in the pair of bit lines, wherein the second state control signal is independent of a pre-charge relating signal externally applied and the pre-charging part cuts-off a supply voltage from being applied to the pair of bit lines with defect; and a bit line floating prevent part for compensatively fixing potential values of the pair of bit lines with defect so that a cell supply voltage is prevented from being applied to the pair of bit lines with defect at a memory access mode of the semiconductor memory device, so that a hard type defect like a stand-by current failure can be repaired regardless of a logic state of a pre-charge control signal, thereby reducing the probability of occurrence of defect in a semiconductor memory device.

摘要翻译： 具有与位线对和字线对连接的存储单元的半导体存储器件包括预充电部分，用于响应于半导体存储器件的待机模式下的第一状态控制信号对一对位线进行预充电 ; 位线充电控制部分，用于当由于一对位线中的缺陷而发生待机电流故障时，向预充电部分产生第二状态控制信号，其中第二状态控制信号独立于预充电 相关信号外部施加，并且预充电部分切断电源电压而不被施加到一对位线; 以及位线浮动防止部件，用于以缺陷补偿地固定一对位线的电位值，使得防止单元电源电压被施加到半导体存储器件的存储器访问模式下的缺陷的位线对， 使得像预备电流故障那样的硬型缺陷可以被修复，而不管预充电控制信号的逻辑状态如何，从而降低了半导体存储器件中的缺陷的发生概率。

公开(公告)号：US07075848B2

公开(公告)日：2006-07-11

申请号：US10889194

申请日：2004-07-12

申请人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

发明人： Byung-Gil Choi ,  Du-Eung Kim ,  Choong-Keun Kwak

IPC分类号： G11C17/18

CPC分类号： G11C29/812 ,  G11C29/806

摘要： A redundancy circuit in a semiconductor memory device having a multiblock structure in which a memory cell array is classified into a plurality of memory cell blocks, an integrated redundancy circuit having a plurality of fuse boxes for storing, per block, addresses of defective memory cells provided in the plurality of memory cell blocks, the plurality of fuse boxes being connected to the common precharge unit and being selectively activated in response to a block distinction selection signal.

摘要翻译： 一种具有多块结构的半结构存储器件中的冗余电路，其中存储单元阵列被分为多个存储单元块，集成冗余电路具有多个保险丝盒，用于存储每块所提供的不良存储器单元的地址 在所述多个存储单元块中，所述多个保险丝盒连接到所述公共预充电单元，并且响应于块区别选择信号被选择性地激活。

公开(公告)号：US06288926B1

公开(公告)日：2001-09-11

申请号：US09535871

申请日：2000-03-27

申请人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

发明人： Du-Eung Kim ,  Byung-Gil Choi ,  Sang-Jib Han ,  Choong-Keun Kwak ,  Soon-Moon Jung ,  Sung-Bong Kim

IPC分类号： G11C506

CPC分类号： G11C5/063 ,  G11C11/412

摘要： A semiconductor memory device is disclosed. The device is comprised of a plurality of word lines; a plurality of bit lines arranged in perpendicular to the word lines. In addition, a plurality of supply voltage lines extend in the same direction as the bit lines. Also, a plurality of first ground voltage lines are arranged in the same direction as the bit lines. Further, a plurality of second ground voltage lines are arranged in the same direction as the word lines. A plurality of memory cells are each connected between one of the word lines and one of the bit lines. Here, the ground voltage lines are arranged in a matrix shape to reduce the resistance of the ground voltage line and secure the margin between the supply voltage level and the ground voltage level of the data latched by the memory cells to thereby prevent an operational failure of the device.

摘要翻译： 公开了一种半导体存储器件。 该装置由多条字线组成; 垂直于字线布置的多个位线。 此外，多个电源电压线沿与位线相同的方向延伸。 此外，多个第一接地电压线被布置在与位线相同的方向上。 此外，多个第二接地电压线布置在与字线相同的方向上。 多个存储单元分别连接在一条字线和一条位线之间。 这里，接地电压线被布置成矩阵形状以减小接地电压线的电阻并且确保由存储器单元锁存的数据的电源电压电平和接地电压电平之间的裕度，从而防止 装置。

公开(公告)号：US5754487A

公开(公告)日：1998-05-19

申请号：US749277

申请日：1996-11-13

申请人： Du-Eung Kim ,  Choong-Keun Kwak ,  Young-Ho Suh ,  Hyun-Geun Byun

发明人： Du-Eung Kim ,  Choong-Keun Kwak ,  Young-Ho Suh ,  Hyun-Geun Byun

IPC分类号： G11C11/41 ,  G11C7/12 ,  G11C11/407 ,  G11C7/00

CPC分类号： G11C7/12

摘要： An SRAM, which includes a plurality of bit line pairs, a memory cell connected between each pair of the bit lines, and an address transition detection circuit for detecting transition of the externally applied address signal to generate a detection pulse signal, is provided with an improved bit line precharge circuit requiring only two transistors per bit line pair. The new precharge circuit is controlled by a bit line precharge control signal generator for generating a control signal determined by a ratio of impedances connected between a source voltage and ground voltage.

摘要翻译： 包括多个位线对的SRAM，连接在每对位线之间的存储单元，以及用于检测外部施加的地址信号的转换以产生检测脉冲信号的地址转换检测电路， 改进的位线预充电电路每位线对只需要两个晶体管。 新的预充电电路由位线预充电控制信号发生器控制，用于产生由源电压和接地电压之间连接的阻抗比确定的控制信号。